Design of an optimized SRM control architecture based on a hardware/software partitioning

This paper presents an effective digital speed control implementation for a switched reluctance machine. An optimized architecture is proposed based on a hardware/software partitioning in order to implement it on a System on Programmable Chip. This solution leads to a user-friendly development solution without over pending for performance or sacrificing features. Finally, the proposed strategy achieves lower current and torque ripples in a large speed range compared to a software implementation.