Framework for massively parallel testing at wafer and package test

Framework for massively parallel testing at wafer and package test

A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Baba, A.H., Kee Sup Kim
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit testing
Hardware
Logic devices
Logic testing
Multiprocessor interconnection networks
Packaging
Pins
Probes
System testing
Very large scale integration
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Beschreibung
Zusammenfassung:A novel DFT approach is introduced that enables massively parallel testing of logic devices at both wafer and package test. Parallelism is achieved by utilizing interconnection networks that are built onto a wafer probe or a tester interface unit. The financial benefits of this method in a realistic setting are also presented.
ISSN:1063-6404
2576-6996
DOI:10.1109/ICCD.2009.5413134