An L-band Fractional-N Synthesizer with Noise-Less Active Capacitor Scaling

In a charge-pump based type-II analog phase locked loop (PLL), the loop filter often uses a small resistor along with a big integrating capacitor for good phase noise performance. This comes at the cost of large silicon area or external component. The noise from the resistor contributes to the output phase noise through both feedback and feed-forward paths and hence has a presence in the output over a very wide frequency band. In this PLL, the loop filter avoids the feed-forward and limits the contribution of the resistor noise over a narrow frequency band. This technique allows a large resistor to be used with a small capacitor without phase noise penalty. The achieved independent control of bandwidth and stabilizing zero gives better stability and reduces noise peaking. The integrated phase error achieved at 1.3 GHz is -38 dBc.