Post Assembly Timing Closure for Multi Million Gate Chips

A hierarchical timing closure methodology is presented. It has timing closure effectiveness of flat methods, while capacity and run time efficiency of subchip based methods. The unique proposition is that it performs flat logic physical optimization of cross subchip timing paths, while at the same time, abides to hierarchy rules. The principle and details of the methodology are provided. Experimental result on multi million gate designs shows its timing closure effectiveness with run time gains of 50% on optimization steps, and peak memory reduction as well.