Effects of interface traps and oxide traps on gate capacitance of MOS devices with ultrathin (EOT ~ 1 nm) high-κ stacked gate dielectrics
A quantum mechanical (QM) self-consistent model is developed for nano-MOS devices for high-κ insulator including wave function penetration effect into the gate dielectrics. The effects of different types of interface trap distributions are incorporated. It has been observed that capacitance-voltage...
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| creator | Sarwar, A.T.M.G. Siddiqui, M.R. Siddique, R.H. Khosru, Q.D.M. |
| description | A quantum mechanical (QM) self-consistent model is developed for nano-MOS devices for high-κ insulator including wave function penetration effect into the gate dielectrics. The effects of different types of interface trap distributions are incorporated. It has been observed that capacitance-voltage (C-V) characteristics are sensitive to the interface trap distribution. Simulated results has been compared with a published result both for uniformly distributed interface traps and without interface traps. Further it is shown that trap charge of oxide dielectrics has also significant effect on C-V characteristics. Finally gate C-V characteristics are presented when both interface traps and oxide traps are present. |
| doi_str_mv | 10.1109/TENCON.2009.5395836 |
| format | Conference Proceeding |
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Finally gate C-V characteristics are presented when both interface traps and oxide traps are present.</description><subject>Capacitance</subject><subject>Capacitance-voltage characteristics</subject><subject>Dielectric devices</subject><subject>Dielectric materials</subject><subject>Dielectric substrates</subject><subject>Dielectrics and electrical insulation</subject><subject>Electron traps</subject><subject>MOS devices</subject><subject>Nanoscale devices</subject><subject>Quantum mechanics</subject><issn>2159-3442</issn><issn>2159-3450</issn><isbn>9781424445462</isbn><isbn>1424445469</isbn><isbn>1424445477</isbn><isbn>9781424445479</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9kMlOwzAQhs1Sibb0CXqZIxxSHC9JfERVWKTSHMi9cr00hjapYrNdeAAeiYfgmQhqy1xGo--fb6RBaBzjSRxjcVXm82kxnxCMxYRTwTOaHKFBzAhjjLM0PUZ9EnMRUcbxCRqJNDuwhJz-M0Z6aPDnEJgKzM7QyPsn3BXHKRakj75ya40KHhoLrg6mtVIZCK3cepC1hubd6cPc1LCSwYCSW6lckHWX7NYeikfQ5tUp4-HNhQpe1l0-VK6Gi7wo4RNiqDeXULlVFf18gw9SPRu9c2ln1t391il_jnpWrr0Z7fsQlTd5Ob2LZsXt_fR6FjmBQ0SUsJYqzYnmjLKECW5kusSSZSKRyTKmXFOWWdtBoS2n2DBFqREyzWwmOR2i8U7rjDGLbes2sv1Y7F9MfwELpWqm</recordid><startdate>200911</startdate><enddate>200911</enddate><creator>Sarwar, A.T.M.G.</creator><creator>Siddiqui, M.R.</creator><creator>Siddique, R.H.</creator><creator>Khosru, Q.D.M.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200911</creationdate><title>Effects of interface traps and oxide traps on gate capacitance of MOS devices with ultrathin (EOT ~ 1 nm) high-κ stacked gate dielectrics</title><author>Sarwar, A.T.M.G. ; Siddiqui, M.R. ; Siddique, R.H. ; Khosru, Q.D.M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-2c9ff3cd52d54346495ea7b0a4896a6b135d348ff4349df530e4c33e9a78f8a53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Capacitance</topic><topic>Capacitance-voltage characteristics</topic><topic>Dielectric devices</topic><topic>Dielectric materials</topic><topic>Dielectric substrates</topic><topic>Dielectrics and electrical insulation</topic><topic>Electron traps</topic><topic>MOS devices</topic><topic>Nanoscale devices</topic><topic>Quantum mechanics</topic><toplevel>online_resources</toplevel><creatorcontrib>Sarwar, A.T.M.G.</creatorcontrib><creatorcontrib>Siddiqui, M.R.</creatorcontrib><creatorcontrib>Siddique, R.H.</creatorcontrib><creatorcontrib>Khosru, Q.D.M.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sarwar, A.T.M.G.</au><au>Siddiqui, M.R.</au><au>Siddique, R.H.</au><au>Khosru, Q.D.M.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Effects of interface traps and oxide traps on gate capacitance of MOS devices with ultrathin (EOT ~ 1 nm) high-κ stacked gate dielectrics</atitle><btitle>TENCON 2009 - 2009 IEEE Region 10 Conference</btitle><stitle>TENCON</stitle><date>2009-11</date><risdate>2009</risdate><spage>1</spage><epage>5</epage><pages>1-5</pages><issn>2159-3442</issn><eissn>2159-3450</eissn><isbn>9781424445462</isbn><isbn>1424445469</isbn><eisbn>1424445477</eisbn><eisbn>9781424445479</eisbn><abstract>A quantum mechanical (QM) self-consistent model is developed for nano-MOS devices for high-κ insulator including wave function penetration effect into the gate dielectrics. The effects of different types of interface trap distributions are incorporated. It has been observed that capacitance-voltage (C-V) characteristics are sensitive to the interface trap distribution. Simulated results has been compared with a published result both for uniformly distributed interface traps and without interface traps. Further it is shown that trap charge of oxide dielectrics has also significant effect on C-V characteristics. Finally gate C-V characteristics are presented when both interface traps and oxide traps are present.</abstract><pub>IEEE</pub><doi>10.1109/TENCON.2009.5395836</doi><tpages>5</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 2159-3442 |
| ispartof | TENCON 2009 - 2009 IEEE Region 10 Conference, 2009, p.1-5 |
| issn | 2159-3442 2159-3450 |
| language | eng |
| recordid | cdi_ieee_primary_5395836 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Capacitance Capacitance-voltage characteristics Dielectric devices Dielectric materials Dielectric substrates Dielectrics and electrical insulation Electron traps MOS devices Nanoscale devices Quantum mechanics |
| title | Effects of interface traps and oxide traps on gate capacitance of MOS devices with ultrathin (EOT ~ 1 nm) high-κ stacked gate dielectrics |
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