Effects of interface traps and oxide traps on gate capacitance of MOS devices with ultrathin (EOT ~ 1 nm) high-κ stacked gate dielectrics

A quantum mechanical (QM) self-consistent model is developed for nano-MOS devices for high-κ insulator including wave function penetration effect into the gate dielectrics. The effects of different types of interface trap distributions are incorporated. It has been observed that capacitance-voltage (C-V) characteristics are sensitive to the interface trap distribution. Simulated results has been compared with a published result both for uniformly distributed interface traps and without interface traps. Further it is shown that trap charge of oxide dielectrics has also significant effect on C-V characteristics. Finally gate C-V characteristics are presented when both interface traps and oxide traps are present.