1-bit sub threshold full adders in 65nm CMOS technology

1-bit sub threshold full adders in 65nm CMOS technology

In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65 nm standarad CMOS models are provided. The simulation results...

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Bibliographische Detailangaben
Hauptverfasser: Moradi, F., Wisland, D.T., Tuan Vu Cao, Peiravi, A., Mahmoodi, H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Adders
Circuit simulation
Circuit topology
CMOS technology
Delay
Dynamic voltage scaling
Energy consumption
Full adder
Low voltage
MOS devices
subthreshold
Threshold voltage
ultra low power
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Beschreibung
Zusammenfassung:In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65 nm standarad CMOS models are provided. The simulation results show a 5%-20% for frequency ranges from 1 KHz to 20 MHz and supply voltages lower than 0.3 V.
ISSN:2159-1660
DOI:10.1109/ICM.2008.5393820