Linear radio frequency power detector

In this paper, a design for high dynamic range applicable of power detector by using successive detection logarithmic amplifier (SDLA) configuration consists of PMOS load limiting amplifier and unbalanced source-coupled pairs. This device was been fabricated by TSMC 0.18-¿m 1P6M CMOS process. The experimental results show that the dynamic range of the power detector the frequency 900-MHz is almost kept at 39-dB and for frequency 1800-MHz, the dynamic range is 29-dB. Its log-error is kept at ±1-dB and consumes is 16-mW from a 1.8-V supply.