Realization of a high-assurance multiplexer using FPGA-based single-chip cryptography

A high assurance multiplexer can be used to combine all channels of a MSLS system into a single stream that accommodates all of the channels to be transported at each end of the multiplexed link. The multiplexer/demultiplexer is termed ¿high assurance¿ because it guarantees the integrity of the channel separation process such that, even under multiple failure conditions, the design assures that data from one channel is not inadvertently mixed with or sent to another channel. Advances in FPGA-based single-chip cryptography design flows and certification agency endorsement policies allow for a whole-new class of information assurance design mechanisms. These design flows verify that separation requirements are met and that additional security qualifications are included as part of the design implementation process. Utilizing the benefits of this new design methodology, an FPGA-based high-assurance multiplexer implementation is realizable.