Automatic test chip documentation synthesis

Automatic test chip documentation synthesis

We describe a new test chip documentation methodology which simultaneously generates inputs for layout design and test chip documentation. On-line test chip documentation is generated based on specifications from the test structure requester/designer. This specification is used as input for both the...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Nagorski, W., McGee, W., Piccioli, E.G., Bair, L.A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Automatic testing
Circuit testing
Design engineering
Documentation
Markup languages
Productivity
Software testing
Standardization
Standards development
Time to market
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Beschreibung
Zusammenfassung:We describe a new test chip documentation methodology which simultaneously generates inputs for layout design and test chip documentation. On-line test chip documentation is generated based on specifications from the test structure requester/designer. This specification is used as input for both the layout designer and also for software which generates on-line test structure documentation. In addition, results from layout and circuit verification tools are compared with specifications to ensure that layout, specification, and documentation agree.
DOI:10.1109/ICMTS.1996.535650