A 295 MHz CMOS 1 M (/spl times/256) embedded SRAM using bi-directional read/write shared sense amps and self-timed pulsed word-line drivers

This SRAM explores the feasibility of the mid-capacity, wideword, very high-speed embedded memories for the over-200 MHz generation of MPUs. The SRAM is fabricated in a 0.35 /spl mu/m CMOS quadruple-metal process. It has 1 Mb capacity and 256 b of full-differential 0.3 V-swing I/O. A bidirectional read/write shared sense amp (BSA) and self-timed pulsed word-line (SPW) are used to reduce power consumption, save chip area, and improve performance.