A 14-port 3.8 ns 116-word 64b read-renaming register file

A 14-port 3.8 ns 116-word 64b read-renaming register file

A 116-word/spl times/64b register file with ten read ports and four write ports is part of a four-issue superscalar, register-renamed, four-window, V9 SPARC-architecture CPU operating at 154MHz. Since the register file combines a register-rename function with the register-read operation, the CPU pip...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Asato, C., Montoye, R., Gmuender, J., Wade Simmons, E., Ike, A., Zasio, J.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Clocks
Decoding
Latches
Logic arrays
Pipelines
Pulse amplifiers
Read only memory
Registers
Switches
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A 116-word/spl times/64b register file with ten read ports and four write ports is part of a four-issue superscalar, register-renamed, four-window, V9 SPARC-architecture CPU operating at 154MHz. Since the register file combines a register-rename function with the register-read operation, the CPU pipeline is one stage shorter than other register-renaming architectures.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.1995.535449