A 210 Mb/s radix-4 bit-level pipelined Viterbi decoder

A 210 Mb/s radix-4 bit-level pipelined Viterbi decoder

The design of a high-speed and compact parallel add-compare-select unit using a combination of algorithmic, logic and circuit techniques is described. The results are demonstrated by a 16-state, R=1/2, 210Mb/s Viterbi decoder, that out-performs the fastest single-chip implementation previously repor...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Yeung, A.K., Rabaey, J.M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
Decoding
Disk drives
Logic design
Pipeline processing
Routing
Sequences
Signal processing
Signal processing algorithms
Viterbi algorithm
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Beschreibung
Zusammenfassung:The design of a high-speed and compact parallel add-compare-select unit using a combination of algorithmic, logic and circuit techniques is described. The results are demonstrated by a 16-state, R=1/2, 210Mb/s Viterbi decoder, that out-performs the fastest single-chip implementation previously reported by a factor of 1.8 in terms of the throughput/area metric using the same process technology.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.1995.535288