A new electrothermally-aware methodology for full-chip temperature optimization
Due to the fact that there is electrothermal coupling between power, delay, and temperature, the paper presents a new electrothermally-aware methodology for full-chip temperature optimization. The main idea is that characteristics of temperature distribution can be improved dramatically by a certain...
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| creator | Gang Dong Peng Leng Changchun Chai Yintang Yang |
| description | Due to the fact that there is electrothermal coupling between power, delay, and temperature, the paper presents a new electrothermally-aware methodology for full-chip temperature optimization. The main idea is that characteristics of temperature distribution can be improved dramatically by a certain given delay penalty. As an example, based on HotSpot, the optimization for AMD Athlon 64 processor in 90-nm technology is given in the paper. Simulation results show that the chip temperature and power optimized by the proposed method are decreased, temperature gradient is also reduced. |
| doi_str_mv | 10.1109/ASICON.2009.5351222 |
| format | Conference Proceeding |
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The main idea is that characteristics of temperature distribution can be improved dramatically by a certain given delay penalty. As an example, based on HotSpot, the optimization for AMD Athlon 64 processor in 90-nm technology is given in the paper. Simulation results show that the chip temperature and power optimized by the proposed method are decreased, temperature gradient is also reduced.</description><identifier>ISSN: 2162-7541</identifier><identifier>ISBN: 9781424438693</identifier><identifier>ISBN: 1424438691</identifier><identifier>ISBN: 1424438683</identifier><identifier>ISBN: 9781424438686</identifier><identifier>EISSN: 2162-755X</identifier><identifier>EISBN: 1424438705</identifier><identifier>EISBN: 9781424438709</identifier><identifier>DOI: 10.1109/ASICON.2009.5351222</identifier><identifier>LCCN: 2009900516</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS technology ; Delay ; Electrothermal coupling ; Electrothermal effects ; Full chip ; Heat transfer ; Integrated circuit interconnections ; Optimization ; Optimization methods ; Repeaters ; Resistance heating ; Temperature ; Thermal resistance</subject><ispartof>2009 IEEE 8th International Conference on ASIC, 2009, p.1268-1271</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5351222$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5351222$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Gang Dong</creatorcontrib><creatorcontrib>Peng Leng</creatorcontrib><creatorcontrib>Changchun Chai</creatorcontrib><creatorcontrib>Yintang Yang</creatorcontrib><title>A new electrothermally-aware methodology for full-chip temperature optimization</title><title>2009 IEEE 8th International Conference on ASIC</title><addtitle>ASICON</addtitle><description>Due to the fact that there is electrothermal coupling between power, delay, and temperature, the paper presents a new electrothermally-aware methodology for full-chip temperature optimization. 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Simulation results show that the chip temperature and power optimized by the proposed method are decreased, temperature gradient is also reduced.</description><subject>CMOS technology</subject><subject>Delay</subject><subject>Electrothermal coupling</subject><subject>Electrothermal effects</subject><subject>Full chip</subject><subject>Heat transfer</subject><subject>Integrated circuit interconnections</subject><subject>Optimization</subject><subject>Optimization methods</subject><subject>Repeaters</subject><subject>Resistance heating</subject><subject>Temperature</subject><subject>Thermal resistance</subject><issn>2162-7541</issn><issn>2162-755X</issn><isbn>9781424438693</isbn><isbn>1424438691</isbn><isbn>1424438683</isbn><isbn>9781424438686</isbn><isbn>1424438705</isbn><isbn>9781424438709</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9UM1uwjAYy36QBqxPwKUv0O7LX9McEdoYEhqHbdJuKE3SkSklVQhC7OnXaWi-2LItH4zQDEOJMciH-etqsXkpCYAsOeWYEHKFJpgRxmgtgF-jMcEVKQTnHzcok6K-ZJWkt_8ZwyM0-d2QABxXdyg7HL5gAOMUCzlGm3m-t6fceqtTDGlnY6e8PxfqpKLNO5t2wQQfPs95G2LeHr0v9M71ebJdb6NKx6EV-uQ6962SC_t7NGqVP9jswlP0_vT4tngu1pvlajFfFw4LngrOwLRUG0MFVFrXpKk1axRII4wEbAwjja103UDTtNoMgnNNBweoFhUWdIpmf7vOWrvto-tUPG8vR9Ef8HRYhg</recordid><startdate>200910</startdate><enddate>200910</enddate><creator>Gang Dong</creator><creator>Peng Leng</creator><creator>Changchun Chai</creator><creator>Yintang Yang</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200910</creationdate><title>A new electrothermally-aware methodology for full-chip temperature optimization</title><author>Gang Dong ; Peng Leng ; Changchun Chai ; Yintang Yang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-540df3cdd3706cc82b8c4ba09d7d901dd42be6c8b0bbfcdc8b55c3e6c03c76173</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>CMOS technology</topic><topic>Delay</topic><topic>Electrothermal coupling</topic><topic>Electrothermal effects</topic><topic>Full chip</topic><topic>Heat transfer</topic><topic>Integrated circuit interconnections</topic><topic>Optimization</topic><topic>Optimization methods</topic><topic>Repeaters</topic><topic>Resistance heating</topic><topic>Temperature</topic><topic>Thermal resistance</topic><toplevel>online_resources</toplevel><creatorcontrib>Gang Dong</creatorcontrib><creatorcontrib>Peng Leng</creatorcontrib><creatorcontrib>Changchun Chai</creatorcontrib><creatorcontrib>Yintang Yang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gang Dong</au><au>Peng Leng</au><au>Changchun Chai</au><au>Yintang Yang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A new electrothermally-aware methodology for full-chip temperature optimization</atitle><btitle>2009 IEEE 8th International Conference on ASIC</btitle><stitle>ASICON</stitle><date>2009-10</date><risdate>2009</risdate><spage>1268</spage><epage>1271</epage><pages>1268-1271</pages><issn>2162-7541</issn><eissn>2162-755X</eissn><isbn>9781424438693</isbn><isbn>1424438691</isbn><isbn>1424438683</isbn><isbn>9781424438686</isbn><eisbn>1424438705</eisbn><eisbn>9781424438709</eisbn><abstract>Due to the fact that there is electrothermal coupling between power, delay, and temperature, the paper presents a new electrothermally-aware methodology for full-chip temperature optimization. The main idea is that characteristics of temperature distribution can be improved dramatically by a certain given delay penalty. As an example, based on HotSpot, the optimization for AMD Athlon 64 processor in 90-nm technology is given in the paper. Simulation results show that the chip temperature and power optimized by the proposed method are decreased, temperature gradient is also reduced.</abstract><pub>IEEE</pub><doi>10.1109/ASICON.2009.5351222</doi><tpages>4</tpages></addata></record> |
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| identifier | ISSN: 2162-7541 |
| ispartof | 2009 IEEE 8th International Conference on ASIC, 2009, p.1268-1271 |
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| language | eng |
| recordid | cdi_ieee_primary_5351222 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS technology Delay Electrothermal coupling Electrothermal effects Full chip Heat transfer Integrated circuit interconnections Optimization Optimization methods Repeaters Resistance heating Temperature Thermal resistance |
| title | A new electrothermally-aware methodology for full-chip temperature optimization |
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