Pin-limited frequency converter IP bridge for efficient communication of automotive IC sensors with off-chip ECUs

Modern automotive electronic systems are based on distributed nets of smart IC sensors, typically implemented as mixed-signal ASICs. Beside the sensing device also the analog front-end, the A/D converter and some DSP processing tasks are integrated in a single-chip. A key issue for these micro-syste...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Saponara, S., Cecchini, T., Sechi, F., Fanucci, L.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Modern automotive electronic systems are based on distributed nets of smart IC sensors, typically implemented as mixed-signal ASICs. Beside the sensing device also the analog front-end, the A/D converter and some DSP processing tasks are integrated in a single-chip. A key issue for these micro-systems is a cost-effective communication with the off-chip Electronic Control Unit (ECU) for correct managing of relative actuators. Due to the limited amount of space and to reduce costs, automotive sensor chips are often pin-limited. Therefore a bridge must be designed to enable efficient communication between the IC and off-chip FPGAs or microcontrollers or DSPs. This operation can be implemented by an internal bus remapping (typically AHB or APB bus are used for embedded systems) on a low-frequency pin-limited external bus. This paper presents the complete design of an IP bridge and its implementation in a real smart sensor system on BCD technology. The proposed architecture is based on bisynchronous FIFO structures for frequency conversion and involves a custom protocol for cost-effective data transmission on a low frequency and low width bus. Different priority levels are also managed. The IP module is APB/AHB compliant, has two handshaking signals and the number of pins is configurable during the implementation phase. Output clock frequency and internal FIFOs size can be defined by the user too.
DOI:10.1109/IDAACS.2009.5343003