A CMOS low power ultra-wideband LNA utilizing feedback technique

A CMOS 3.1-10.6GHz low power low noise amplifier utilizing a feedback technique is reported. The series-inductive peaking has been used in the output stage to improve the 3-dB bandwidth of the LNA. To achieve wide and stable power and noise matching, the frequency dependent Miller multiplication factors, combined with a new parallel input inductor, is employed. The design is implemented in standard 0.13µm CMOS process. The LNA dissipates only 5.2mW power while it achieves a maximum power gain of 7.5dB, input return loss of better than −8dB and noise figure of 6.5-7.8 dB over the band of interest. The very small power consumption of this design makes it ideal for RFID applications. The chip area is only 700×1000µm including all test pads and ESD protection.