System Performance Analyses on PAC Duo ESL Virtual Platform
The trend towards heterogeneous multi-core integration and higher communication bandwidth drastically increases the complexity of the SoC. Architecture design and system validation become extremely challenging. This paper presents a system-level virtual platform and simulation environment for multi-...
Gespeichert in:
| Hauptverfasser: | , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 409 |
|---|---|
| container_issue | |
| container_start_page | 406 |
| container_title | |
| container_volume | |
| creator | Zhe-Mao Hsu I-Yao Chuang Wen-Chien Su Jen-Chieh Yeh Jen-Kuei Yang Shau-Yin Tseng |
| description | The trend towards heterogeneous multi-core integration and higher communication bandwidth drastically increases the complexity of the SoC. Architecture design and system validation become extremely challenging. This paper presents a system-level virtual platform and simulation environment for multi-core system performance profiling and evaluation. At the higher level of abstraction, we implement a fast and high accurate dual DSP virtual platform for multimedia application. The simulation speed of this platform can achieve 100 times faster than RTL and the timing accuracy can maintain above 90%. Based on this virtual platform, the system function and performance analyses can be realized. We propose the performance metrics to analyze dual core system bottleneck. Experiments show that the virtual platform helps the system evaluation and exploration. The virtual platform can assist software and hardware engineers to scrutinize application efficiency and architecture evaluation respectively. |
| doi_str_mv | 10.1109/IIH-MSP.2009.86 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5337512</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5337512</ieee_id><sourcerecordid>5337512</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-12c9d523c01abd881800342d5b088a4d2fab2f5806f8902bd02c5a6468e396243</originalsourceid><addsrcrecordid>eNotjMlKxEAURUtEUNqsXbipH0h89WrGVYitHYgYSOO2qSQViGSQVHqRv3e8m8OBwyXkjkHCGNiHPD_Er1WZIIBNjLogkdUGtLKSa4X68teZQCGEZlpdkyiED_iekFwydkMeqy2sfqSlX7p5Gd3UeJpObtiCD3SeaJlm9Ok8031V0Pd-Wc9uoOXg1p_4llx1bgg--ueOHJ_3x-wQF28veZYWcW9hjRk2tpXIG2Cubo1hBoALbGUNxjjRYudq7KQB1RkLWLeAjXRKKOO5VSj4jtz_3fbe-9Pn0o9u2U6Scy0Z8i9u4UbX</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>System Performance Analyses on PAC Duo ESL Virtual Platform</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Zhe-Mao Hsu ; I-Yao Chuang ; Wen-Chien Su ; Jen-Chieh Yeh ; Jen-Kuei Yang ; Shau-Yin Tseng</creator><creatorcontrib>Zhe-Mao Hsu ; I-Yao Chuang ; Wen-Chien Su ; Jen-Chieh Yeh ; Jen-Kuei Yang ; Shau-Yin Tseng</creatorcontrib><description>The trend towards heterogeneous multi-core integration and higher communication bandwidth drastically increases the complexity of the SoC. Architecture design and system validation become extremely challenging. This paper presents a system-level virtual platform and simulation environment for multi-core system performance profiling and evaluation. At the higher level of abstraction, we implement a fast and high accurate dual DSP virtual platform for multimedia application. The simulation speed of this platform can achieve 100 times faster than RTL and the timing accuracy can maintain above 90%. Based on this virtual platform, the system function and performance analyses can be realized. We propose the performance metrics to analyze dual core system bottleneck. Experiments show that the virtual platform helps the system evaluation and exploration. The virtual platform can assist software and hardware engineers to scrutinize application efficiency and architecture evaluation respectively.</description><identifier>ISBN: 9781424447176</identifier><identifier>ISBN: 1424447178</identifier><identifier>EISBN: 9780769537627</identifier><identifier>EISBN: 0769537626</identifier><identifier>DOI: 10.1109/IIH-MSP.2009.86</identifier><language>eng</language><publisher>IEEE</publisher><subject>Accuracy ; Application software ; Bandwidth ; Digital signal processing ; electronic system-level (ESL) ; Hardware ; Maintenance engineering ; Measurement ; Performance analysis ; System performance ; Timing ; virtual platform</subject><ispartof>2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2009, p.406-409</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5337512$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5337512$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zhe-Mao Hsu</creatorcontrib><creatorcontrib>I-Yao Chuang</creatorcontrib><creatorcontrib>Wen-Chien Su</creatorcontrib><creatorcontrib>Jen-Chieh Yeh</creatorcontrib><creatorcontrib>Jen-Kuei Yang</creatorcontrib><creatorcontrib>Shau-Yin Tseng</creatorcontrib><title>System Performance Analyses on PAC Duo ESL Virtual Platform</title><title>2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing</title><addtitle>IIHMSP</addtitle><description>The trend towards heterogeneous multi-core integration and higher communication bandwidth drastically increases the complexity of the SoC. Architecture design and system validation become extremely challenging. This paper presents a system-level virtual platform and simulation environment for multi-core system performance profiling and evaluation. At the higher level of abstraction, we implement a fast and high accurate dual DSP virtual platform for multimedia application. The simulation speed of this platform can achieve 100 times faster than RTL and the timing accuracy can maintain above 90%. Based on this virtual platform, the system function and performance analyses can be realized. We propose the performance metrics to analyze dual core system bottleneck. Experiments show that the virtual platform helps the system evaluation and exploration. The virtual platform can assist software and hardware engineers to scrutinize application efficiency and architecture evaluation respectively.</description><subject>Accuracy</subject><subject>Application software</subject><subject>Bandwidth</subject><subject>Digital signal processing</subject><subject>electronic system-level (ESL)</subject><subject>Hardware</subject><subject>Maintenance engineering</subject><subject>Measurement</subject><subject>Performance analysis</subject><subject>System performance</subject><subject>Timing</subject><subject>virtual platform</subject><isbn>9781424447176</isbn><isbn>1424447178</isbn><isbn>9780769537627</isbn><isbn>0769537626</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjMlKxEAURUtEUNqsXbipH0h89WrGVYitHYgYSOO2qSQViGSQVHqRv3e8m8OBwyXkjkHCGNiHPD_Er1WZIIBNjLogkdUGtLKSa4X68teZQCGEZlpdkyiED_iekFwydkMeqy2sfqSlX7p5Gd3UeJpObtiCD3SeaJlm9Ok8031V0Pd-Wc9uoOXg1p_4llx1bgg--ueOHJ_3x-wQF28veZYWcW9hjRk2tpXIG2Cubo1hBoALbGUNxjjRYudq7KQB1RkLWLeAjXRKKOO5VSj4jtz_3fbe-9Pn0o9u2U6Scy0Z8i9u4UbX</recordid><startdate>200909</startdate><enddate>200909</enddate><creator>Zhe-Mao Hsu</creator><creator>I-Yao Chuang</creator><creator>Wen-Chien Su</creator><creator>Jen-Chieh Yeh</creator><creator>Jen-Kuei Yang</creator><creator>Shau-Yin Tseng</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200909</creationdate><title>System Performance Analyses on PAC Duo ESL Virtual Platform</title><author>Zhe-Mao Hsu ; I-Yao Chuang ; Wen-Chien Su ; Jen-Chieh Yeh ; Jen-Kuei Yang ; Shau-Yin Tseng</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-12c9d523c01abd881800342d5b088a4d2fab2f5806f8902bd02c5a6468e396243</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Accuracy</topic><topic>Application software</topic><topic>Bandwidth</topic><topic>Digital signal processing</topic><topic>electronic system-level (ESL)</topic><topic>Hardware</topic><topic>Maintenance engineering</topic><topic>Measurement</topic><topic>Performance analysis</topic><topic>System performance</topic><topic>Timing</topic><topic>virtual platform</topic><toplevel>online_resources</toplevel><creatorcontrib>Zhe-Mao Hsu</creatorcontrib><creatorcontrib>I-Yao Chuang</creatorcontrib><creatorcontrib>Wen-Chien Su</creatorcontrib><creatorcontrib>Jen-Chieh Yeh</creatorcontrib><creatorcontrib>Jen-Kuei Yang</creatorcontrib><creatorcontrib>Shau-Yin Tseng</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zhe-Mao Hsu</au><au>I-Yao Chuang</au><au>Wen-Chien Su</au><au>Jen-Chieh Yeh</au><au>Jen-Kuei Yang</au><au>Shau-Yin Tseng</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>System Performance Analyses on PAC Duo ESL Virtual Platform</atitle><btitle>2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing</btitle><stitle>IIHMSP</stitle><date>2009-09</date><risdate>2009</risdate><spage>406</spage><epage>409</epage><pages>406-409</pages><isbn>9781424447176</isbn><isbn>1424447178</isbn><eisbn>9780769537627</eisbn><eisbn>0769537626</eisbn><abstract>The trend towards heterogeneous multi-core integration and higher communication bandwidth drastically increases the complexity of the SoC. Architecture design and system validation become extremely challenging. This paper presents a system-level virtual platform and simulation environment for multi-core system performance profiling and evaluation. At the higher level of abstraction, we implement a fast and high accurate dual DSP virtual platform for multimedia application. The simulation speed of this platform can achieve 100 times faster than RTL and the timing accuracy can maintain above 90%. Based on this virtual platform, the system function and performance analyses can be realized. We propose the performance metrics to analyze dual core system bottleneck. Experiments show that the virtual platform helps the system evaluation and exploration. The virtual platform can assist software and hardware engineers to scrutinize application efficiency and architecture evaluation respectively.</abstract><pub>IEEE</pub><doi>10.1109/IIH-MSP.2009.86</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9781424447176 |
| ispartof | 2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2009, p.406-409 |
| issn | |
| language | eng |
| recordid | cdi_ieee_primary_5337512 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Accuracy Application software Bandwidth Digital signal processing electronic system-level (ESL) Hardware Maintenance engineering Measurement Performance analysis System performance Timing virtual platform |
| title | System Performance Analyses on PAC Duo ESL Virtual Platform |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T07%3A48%3A33IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=System%20Performance%20Analyses%20on%20PAC%20Duo%20ESL%20Virtual%20Platform&rft.btitle=2009%20Fifth%20International%20Conference%20on%20Intelligent%20Information%20Hiding%20and%20Multimedia%20Signal%20Processing&rft.au=Zhe-Mao%20Hsu&rft.date=2009-09&rft.spage=406&rft.epage=409&rft.pages=406-409&rft.isbn=9781424447176&rft.isbn_list=1424447178&rft_id=info:doi/10.1109/IIH-MSP.2009.86&rft_dat=%3Cieee_6IE%3E5337512%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9780769537627&rft.eisbn_list=0769537626&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5337512&rfr_iscdi=true |