A deep trench isolation integrated in a 0.13um BiCD process technology for analog power ICs
This paper presents a 0.13 um BiCD process (BiCD-0.13) based on a 0.13 um standard CMOS technology with a superior Deep Trench Isolation(DTI). Merits of using DTI are to improve breakdown voltage, reduce parasitic transistor actions and increase area density, compared with Junction-Isolation. We sim...
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| creator | Kitahara, H. Tsukihara, T. Sakai, M. Morioka, J. Deguchi, K. Yonemura, K. Kikuchi, T. Onoue, S. Shirai, K. Watanabe, K. Kimura, K. |
| description | This paper presents a 0.13 um BiCD process (BiCD-0.13) based on a 0.13 um standard CMOS technology with a superior Deep Trench Isolation(DTI). Merits of using DTI are to improve breakdown voltage, reduce parasitic transistor actions and increase area density, compared with Junction-Isolation. We simulated the stress and the device characteristics, and optimized the parameters of DTI design and process steps. It has been successfully developed the process integration of DTI into 0.13 um process technology with various kinds of HV devices including ultra-low on resistance LDMOS. |
| doi_str_mv | 10.1109/BIPOL.2009.5314160 |
| format | Conference Proceeding |
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It has been successfully developed the process integration of DTI into 0.13 um process technology with various kinds of HV devices including ultra-low on resistance LDMOS.</description><subject>Analog integrated circuits</subject><subject>Automotive engineering</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Costs</subject><subject>Deep Trench Isolation</subject><subject>Diffusion tensor imaging</subject><subject>Diodes</subject><subject>Isolation technology</subject><subject>LDMOS</subject><subject>power devices</subject><subject>Power integrated circuits</subject><subject>Silicon bipolar/BiCMOS process technology</subject><subject>Voltage</subject><issn>1088-9299</issn><issn>2378-590X</issn><isbn>9781424448944</isbn><isbn>1424448948</isbn><isbn>1424448964</isbn><isbn>9781424448968</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kM1Kw0AUhcc_sK19Ad3MC6TeO3OTySzb-Bco1IWC4KJMkps20iZhJiJ9ewvW1fngwMfhCHGLMEMEe7_IX1fLmQKws1gjYQJnYoykiCi1CZ2LkdImjWILHxdiak363xFdihFCmkZWWXstxiF8AShQJh2Jz7msmHs5eG7LrWxCt3ND07WyaQfeeDdwdUTp5HGF_t7LRZM9yN53JYcgBy63bbfrNgdZd1661h1Z9t0Pe5ln4UZc1W4XeHrKiXh_enzLXqLl6jnP5suoUYRDxAY0ORsnlaPY1i6Bqk4LVqg1VqjQEBiuDNWOjSFXaMSyqHQBylJRGtQTcffnbZh53ftm7_xhfTpJ_wLMjFYm</recordid><startdate>200910</startdate><enddate>200910</enddate><creator>Kitahara, H.</creator><creator>Tsukihara, T.</creator><creator>Sakai, M.</creator><creator>Morioka, J.</creator><creator>Deguchi, K.</creator><creator>Yonemura, K.</creator><creator>Kikuchi, T.</creator><creator>Onoue, S.</creator><creator>Shirai, K.</creator><creator>Watanabe, K.</creator><creator>Kimura, K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200910</creationdate><title>A deep trench isolation integrated in a 0.13um BiCD process technology for analog power ICs</title><author>Kitahara, H. ; Tsukihara, T. ; Sakai, M. ; Morioka, J. ; Deguchi, K. ; Yonemura, K. ; Kikuchi, T. ; Onoue, S. ; Shirai, K. ; Watanabe, K. ; Kimura, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i241t-e7034a956da459fa60df8be21331d1217407ed74fae774ab311cbd3b0294bc713</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Analog integrated circuits</topic><topic>Automotive engineering</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Costs</topic><topic>Deep Trench Isolation</topic><topic>Diffusion tensor imaging</topic><topic>Diodes</topic><topic>Isolation technology</topic><topic>LDMOS</topic><topic>power devices</topic><topic>Power integrated circuits</topic><topic>Silicon bipolar/BiCMOS process technology</topic><topic>Voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Kitahara, H.</creatorcontrib><creatorcontrib>Tsukihara, T.</creatorcontrib><creatorcontrib>Sakai, M.</creatorcontrib><creatorcontrib>Morioka, J.</creatorcontrib><creatorcontrib>Deguchi, K.</creatorcontrib><creatorcontrib>Yonemura, K.</creatorcontrib><creatorcontrib>Kikuchi, T.</creatorcontrib><creatorcontrib>Onoue, S.</creatorcontrib><creatorcontrib>Shirai, K.</creatorcontrib><creatorcontrib>Watanabe, K.</creatorcontrib><creatorcontrib>Kimura, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kitahara, H.</au><au>Tsukihara, T.</au><au>Sakai, M.</au><au>Morioka, J.</au><au>Deguchi, K.</au><au>Yonemura, K.</au><au>Kikuchi, T.</au><au>Onoue, S.</au><au>Shirai, K.</au><au>Watanabe, K.</au><au>Kimura, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A deep trench isolation integrated in a 0.13um BiCD process technology for analog power ICs</atitle><btitle>2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting</btitle><stitle>BIPOL</stitle><date>2009-10</date><risdate>2009</risdate><spage>206</spage><epage>209</epage><pages>206-209</pages><issn>1088-9299</issn><eissn>2378-590X</eissn><isbn>9781424448944</isbn><isbn>1424448948</isbn><eisbn>1424448964</eisbn><eisbn>9781424448968</eisbn><abstract>This paper presents a 0.13 um BiCD process (BiCD-0.13) based on a 0.13 um standard CMOS technology with a superior Deep Trench Isolation(DTI). Merits of using DTI are to improve breakdown voltage, reduce parasitic transistor actions and increase area density, compared with Junction-Isolation. We simulated the stress and the device characteristics, and optimized the parameters of DTI design and process steps. It has been successfully developed the process integration of DTI into 0.13 um process technology with various kinds of HV devices including ultra-low on resistance LDMOS.</abstract><pub>IEEE</pub><doi>10.1109/BIPOL.2009.5314160</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1088-9299 |
| ispartof | 2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2009, p.206-209 |
| issn | 1088-9299 2378-590X |
| language | eng |
| recordid | cdi_ieee_primary_5314160 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Analog integrated circuits Automotive engineering CMOS process CMOS technology Costs Deep Trench Isolation Diffusion tensor imaging Diodes Isolation technology LDMOS power devices Power integrated circuits Silicon bipolar/BiCMOS process technology Voltage |
| title | A deep trench isolation integrated in a 0.13um BiCD process technology for analog power ICs |
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