Technology impact analysis for 3D TCAM

In our previous work, 3D TCAMs were designed and evaluated with different 3D partitioning schemes showing that a 40% reduction in matchline interconnect capacitance, 21% power reduction, and 25% reduction in precharge time is achieved in TCAM memory array in 3-tier design based on MIT Lincoln Labs 3...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Eun Chu Oh, Franzon, P.D.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	3D IC 3D intertier via 3D TCAM 3D technology analysis Associative memory Capacitance content addressable memory Decoding Driver circuits Energy consumption Integrated circuit interconnections Logic low power TCAM matchline capacitance Metallization Multilevel systems Three-dimensional integrated circuits vertical interconnect
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Schreiben Sie den ersten Kommentar!