Technology impact analysis for 3D TCAM

In our previous work, 3D TCAMs were designed and evaluated with different 3D partitioning schemes showing that a 40% reduction in matchline interconnect capacitance, 21% power reduction, and 25% reduction in precharge time is achieved in TCAM memory array in 3-tier design based on MIT Lincoln Labs 3D IC process compared to a single-tier design. In this paper, we expand the exploration of the 3D TCAM design in various 3D IC technologies to show how the variations of technology parameters impact the benefits of 3D IC on TCAM. The impact of technology parameters including the number of wafer stacks, 3D via size, metal extension for 3D via alignment, and 3D via deposition order is evaluated in terms of interconnect capacitance and resistance in 3D TCAM designs.