Technology impact analysis for 3D TCAM
In our previous work, 3D TCAMs were designed and evaluated with different 3D partitioning schemes showing that a 40% reduction in matchline interconnect capacitance, 21% power reduction, and 25% reduction in precharge time is achieved in TCAM memory array in 3-tier design based on MIT Lincoln Labs 3...
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| creator | Eun Chu Oh Franzon, P.D. |
| description | In our previous work, 3D TCAMs were designed and evaluated with different 3D partitioning schemes showing that a 40% reduction in matchline interconnect capacitance, 21% power reduction, and 25% reduction in precharge time is achieved in TCAM memory array in 3-tier design based on MIT Lincoln Labs 3D IC process compared to a single-tier design. In this paper, we expand the exploration of the 3D TCAM design in various 3D IC technologies to show how the variations of technology parameters impact the benefits of 3D IC on TCAM. The impact of technology parameters including the number of wafer stacks, 3D via size, metal extension for 3D via alignment, and 3D via deposition order is evaluated in terms of interconnect capacitance and resistance in 3D TCAM designs. |
| doi_str_mv | 10.1109/3DIC.2009.5306563 |
| format | Conference Proceeding |
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In this paper, we expand the exploration of the 3D TCAM design in various 3D IC technologies to show how the variations of technology parameters impact the benefits of 3D IC on TCAM. The impact of technology parameters including the number of wafer stacks, 3D via size, metal extension for 3D via alignment, and 3D via deposition order is evaluated in terms of interconnect capacitance and resistance in 3D TCAM designs.</description><identifier>ISBN: 9781424445110</identifier><identifier>ISBN: 1424445116</identifier><identifier>EISBN: 1424445124</identifier><identifier>EISBN: 9781424445127</identifier><identifier>DOI: 10.1109/3DIC.2009.5306563</identifier><identifier>LCCN: 2009903601</identifier><language>eng</language><publisher>IEEE</publisher><subject>3D IC ; 3D intertier via ; 3D TCAM ; 3D technology analysis ; Associative memory ; Capacitance ; content addressable memory ; Decoding ; Driver circuits ; Energy consumption ; Integrated circuit interconnections ; Logic ; low power TCAM ; matchline capacitance ; Metallization ; Multilevel systems ; Three-dimensional integrated circuits ; vertical interconnect</subject><ispartof>2009 IEEE International Conference on 3D System Integration, 2009, p.1-5</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5306563$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5306563$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Eun Chu Oh</creatorcontrib><creatorcontrib>Franzon, P.D.</creatorcontrib><title>Technology impact analysis for 3D TCAM</title><title>2009 IEEE International Conference on 3D System Integration</title><addtitle>3DIC</addtitle><description>In our previous work, 3D TCAMs were designed and evaluated with different 3D partitioning schemes showing that a 40% reduction in matchline interconnect capacitance, 21% power reduction, and 25% reduction in precharge time is achieved in TCAM memory array in 3-tier design based on MIT Lincoln Labs 3D IC process compared to a single-tier design. In this paper, we expand the exploration of the 3D TCAM design in various 3D IC technologies to show how the variations of technology parameters impact the benefits of 3D IC on TCAM. The impact of technology parameters including the number of wafer stacks, 3D via size, metal extension for 3D via alignment, and 3D via deposition order is evaluated in terms of interconnect capacitance and resistance in 3D TCAM designs.</description><subject>3D IC</subject><subject>3D intertier via</subject><subject>3D TCAM</subject><subject>3D technology analysis</subject><subject>Associative memory</subject><subject>Capacitance</subject><subject>content addressable memory</subject><subject>Decoding</subject><subject>Driver circuits</subject><subject>Energy consumption</subject><subject>Integrated circuit interconnections</subject><subject>Logic</subject><subject>low power TCAM</subject><subject>matchline capacitance</subject><subject>Metallization</subject><subject>Multilevel systems</subject><subject>Three-dimensional integrated circuits</subject><subject>vertical interconnect</subject><isbn>9781424445110</isbn><isbn>1424445116</isbn><isbn>1424445124</isbn><isbn>9781424445127</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1Tz1PwzAUNEKVoCU_ALFkYkt49nu247FK-ahUxJK9cpwXCEqbKu6Sf08Q5ZbT6U53OiHuJeRSgnvCzbbMFYDLNYLRBq_EUpIiIi0VXYvE2eJfS1iI5W_WARqQNyKJ8RtmkFaOilvxWHH4Og798Dml3eHkwzn1R99PsYtpO4wpbtKqXL_fiUXr-8jJhVeienmuyrds9_G6Lde7rHNwzpACMnqjrVXIZt4AVqrwYFoTmtkIaOsmUDCWWg0Nc2vq2jXWGmAkiyvx8FfbMfP-NHYHP077y038AWi1QVQ</recordid><startdate>200909</startdate><enddate>200909</enddate><creator>Eun Chu Oh</creator><creator>Franzon, P.D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200909</creationdate><title>Technology impact analysis for 3D TCAM</title><author>Eun Chu Oh ; Franzon, P.D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-34c3e3a657723e64520e228a06f6cd3a6c37bdc4c674f50deef6bb9d7760e3473</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>3D IC</topic><topic>3D intertier via</topic><topic>3D TCAM</topic><topic>3D technology analysis</topic><topic>Associative memory</topic><topic>Capacitance</topic><topic>content addressable memory</topic><topic>Decoding</topic><topic>Driver circuits</topic><topic>Energy consumption</topic><topic>Integrated circuit interconnections</topic><topic>Logic</topic><topic>low power TCAM</topic><topic>matchline capacitance</topic><topic>Metallization</topic><topic>Multilevel systems</topic><topic>Three-dimensional integrated circuits</topic><topic>vertical interconnect</topic><toplevel>online_resources</toplevel><creatorcontrib>Eun Chu Oh</creatorcontrib><creatorcontrib>Franzon, P.D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Eun Chu Oh</au><au>Franzon, P.D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Technology impact analysis for 3D TCAM</atitle><btitle>2009 IEEE International Conference on 3D System Integration</btitle><stitle>3DIC</stitle><date>2009-09</date><risdate>2009</risdate><spage>1</spage><epage>5</epage><pages>1-5</pages><isbn>9781424445110</isbn><isbn>1424445116</isbn><eisbn>1424445124</eisbn><eisbn>9781424445127</eisbn><abstract>In our previous work, 3D TCAMs were designed and evaluated with different 3D partitioning schemes showing that a 40% reduction in matchline interconnect capacitance, 21% power reduction, and 25% reduction in precharge time is achieved in TCAM memory array in 3-tier design based on MIT Lincoln Labs 3D IC process compared to a single-tier design. In this paper, we expand the exploration of the 3D TCAM design in various 3D IC technologies to show how the variations of technology parameters impact the benefits of 3D IC on TCAM. The impact of technology parameters including the number of wafer stacks, 3D via size, metal extension for 3D via alignment, and 3D via deposition order is evaluated in terms of interconnect capacitance and resistance in 3D TCAM designs.</abstract><pub>IEEE</pub><doi>10.1109/3DIC.2009.5306563</doi><tpages>5</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | 3D IC 3D intertier via 3D TCAM 3D technology analysis Associative memory Capacitance content addressable memory Decoding Driver circuits Energy consumption Integrated circuit interconnections Logic low power TCAM matchline capacitance Metallization Multilevel systems Three-dimensional integrated circuits vertical interconnect |
| title | Technology impact analysis for 3D TCAM |
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