Robust verification of 3D-ICs: Pros, cons and recommendations

Robust verification of 3D-ICs: Pros, cons and recommendations

A robust verification methodology for 3D-IC design is presented. This approach addresses the challenge of delivering a familiar verification solution with minimal disruption to existing design and verification flows. The proposed method provides a generic framework that allows users to specify their...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Hogan, M., Petranovic, D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
3D-IC
Costs
Design methodology
Frequency
integrated circuits
Production
Robustness
Routing
Three-dimensional integrated circuits
through-silicon via
Through-silicon vias
Throughput
TSV
verification
Wafer bonding
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Beschreibung
Zusammenfassung:A robust verification methodology for 3D-IC design is presented. This approach addresses the challenge of delivering a familiar verification solution with minimal disruption to existing design and verification flows. The proposed method provides a generic framework that allows users to specify their own 3D-IC design stacks for verification with TSVs, flip-chips or wire-bonded dies.
DOI:10.1109/3DIC.2009.5306522