nand Gate Design for Ballistic Deflection Transistors

This paper presents a nand gate designed using ballistic deflection transistors (BDTs). Room temperature BDT measurements are captured in an empirical device model to simulate multi-BDT logic design. Measurements from a fabricated BDT nand gate validate the multidevice model and demonstrate the prom...

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Veröffentlicht in:	IEEE transactions on nanotechnology 2011-01, Vol.10 (1), p.150-154
Hauptverfasser:	Wolpert, David, Diduck, Quentin, Ampadu, Paul
Format:	Artikel
Sprache:	eng
Schlagworte:	2-D electron gas (2-DEG) Applied sciences Ballistic transport Circuit design Circuit properties Circuit simulation Circuit synthesis Deflection device model Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Electrons Etching Exact sciences and technology Gates (circuits) Logic design Nanocomposites Nanomaterials Nanostructure Permission quasi-ballistic transport Semiconductor devices Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Temperature measurement Transistors Voltage
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Beschreibung
Zusammenfassung:	This paper presents a nand gate designed using ballistic deflection transistors (BDTs). Room temperature BDT measurements are captured in an empirical device model to simulate multi-BDT logic design. Measurements from a fabricated BDT nand gate validate the multidevice model and demonstrate the promise of BDTs for nanoscale circuit design.
ISSN:	1536-125X 1941-0085
DOI:	10.1109/TNANO.2009.2034962