A 900-mV Area-Efficient Source-Degenerated CMOS Four-Quadrant Multiplier with 10.6-GHz Bandwidth

A 900-mV Area-Efficient Source-Degenerated CMOS Four-Quadrant Multiplier with 10.6-GHz Bandwidth

This paper presents a low-voltage area-efficient four-quadrant CMOS multiplier reconfigured in a source-degenerated topology and designed as a part of a correlator for an integrated ultra-wideband (UWB) transceiver. The simulation based on a 0.18-mum CMOS technology shows that the multiplier offers...

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Hauptverfasser: Sigit Yuwono, Sok-Kyun Han, Sang-Gug Lee
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Circuit topology
CMOS technology
Correlators
Design engineering
Inductors
Radio frequency
Transceivers
Ultra wideband technology
Voltage
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Beschreibung
Zusammenfassung:This paper presents a low-voltage area-efficient four-quadrant CMOS multiplier reconfigured in a source-degenerated topology and designed as a part of a correlator for an integrated ultra-wideband (UWB) transceiver. The simulation based on a 0.18-mum CMOS technology shows that the multiplier offers 10.6-GHz bandwidth while dissipating 290 muA from a 0.9-V supply.
ISSN:2161-9646
DOI:10.1109/WICOM.2009.5305750