A High-Speed 2-D IDCT Processor for Image/Video Decoding

In this paper, a high-speed two dimensional (2D) inverse discrete cosine transform (DDCT) processor for image/video decoding applications is presented. The processor uses row-column approach to calculate 2D DDCT, such that the whole architecture is divided into two 1D DDCT calculations by using a transpose buffer. The 1D DDCT calculation is made using the Loeffler algorithm, and its multiplications are all made using additions and shifts. Pipelining is introduced in the circuit design to make data disposed in parallel. In order to obtain a higher operating frequency, the improved Loeffler algorithm is introduced. Considering that many elements in practical input matrixes are zeros, a row preprocess module is designed to dispose input rows of which the value of last seven elements are zeros. Because of this, the decoding speed of 2D DDCT processor is increased evidently. The high speed 2D IDCT processor uses 5,015 logic elements of one Altera EP2C20F484C7 FPGA and reaches an operating frequency of 117.37 MHz.