A new high-resolution Time-to-Digital Converter concept based on a 128 stage 0.35 µm CMOS delay generator

A stable, sub-nanosecond delay generator is presented. Integrated in conventional low-cost 0.35 mum CMOS technology, the circuit consists of a mirror delay line driven by a dual-loop Delay-Locked Loop (DLL) and a 128-deep analog frame memory. As a practical application of the delay generator, a comp...

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Hauptverfasser:	Zlatanski, M., Uhring, W., Le Normand, J.-P., Zint, V.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Analytical models Circuit optimization Circuit simulation CMOS technology Computational modeling Delay Linear approximation Monte Carlo methods Performance analysis Response surface methodology
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Beschreibung
Zusammenfassung:	A stable, sub-nanosecond delay generator is presented. Integrated in conventional low-cost 0.35 mum CMOS technology, the circuit consists of a mirror delay line driven by a dual-loop Delay-Locked Loop (DLL) and a 128-deep analog frame memory. As a practical application of the delay generator, a completely new, high-resolution, Time-to-Digital Converter (TDC) concept is implemented on-chip. A simulated 20 ps resolution is achieved. A delay stability self-characterization mode was also integrated and showed a 1 GHz sine wave sampled at 8 Gs/s.
DOI:	10.1109/NEWCAS.2009.5290425