A 3-level PWM ADSL2+ CO line driver

A 3-level PWM ADSL2+ CO line driver

A PWM ADSL2+ line driver with 2.2 MHz signal bandwidth is realized in a 3 metal, 2 poly 0.35 mum CMOS process. A low 8.832 MHz switching frequency is used with filtering in the feedback path to suppress aliasing. Signal processing and triangular wave generation are combined in the forward integrator...

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Bibliographische Detailangaben
Hauptverfasser: Gierkink, S., Lakshmikumar, K., Mukundagiri, V., Lim, D., Muralt, A., Larsen, F.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
CMOS process
CMOS technology
Driver circuits
Feedback
Low pass filters
OFDM modulation
Pulse width modulation
Signal processing
Switching frequency
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Beschreibung
Zusammenfassung:A PWM ADSL2+ line driver with 2.2 MHz signal bandwidth is realized in a 3 metal, 2 poly 0.35 mum CMOS process. A low 8.832 MHz switching frequency is used with filtering in the feedback path to suppress aliasing. Signal processing and triangular wave generation are combined in the forward integrators. The driver delivers 100 mW to a 100 Omega line with an MTPR less than -52 dB. Active area is 3 mm 2 .
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2009.5280764