Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application

The proposed on-die termination (ODT) calibration method is implemented by using a 0.18 mum CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2 Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2 Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7 V to 1.9 V. The ODT and its calibration circuit occupy 0.003 mm 2 and 0.015 mm 2 , respectively. The power consumption of the calibration circuit is 10 mW at 2 Gbps.