ESD design challenges and strategies in deeply-scaled integrated circuits

ESD design challenges and strategies in deeply-scaled integrated circuits

Challenges of design window shrinkage in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O and ESD devices, and by developing ESD robustness and circuit performance co-design methodologies. Advanced ESD metrology methods are reviewed and thei...

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Bibliographische Detailangaben
Hauptverfasser: Shuqing Cao, Tze Wee Chen, Beebe, S.G., Dutton, R.W.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
charged device model (CDM)
co-design methodology
Electrostatic discharge
electrostatic discharge (ESD)
field effect diode
high-speed I/O
integrated circuit reliability
semiconductor diodes
VF-TLP
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Beschreibung
Zusammenfassung:Challenges of design window shrinkage in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O and ESD devices, and by developing ESD robustness and circuit performance co-design methodologies. Advanced ESD metrology methods are reviewed and their applications in providing key information for reliability modeling are investigated. Package and wafer level CDM correlation issues are examined.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2009.5280727