LUDMOS transistors optimization on a 0.18um SOI CMOS technology

LUDMOS transistors optimization on a 0.18um SOI CMOS technology

This paper is focused on the design and optimization of power LDMOS transistors with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 mum SOI-CMOS technology. Different LDMOS structures which allow breakdown voltages (V BR ) higher than 120 V have been...

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Hauptverfasser: Toulon, G., Cortes, I., Morancho, F., Villard, B.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS technology
Degradation
Indium phosphide
Isolation technology
MOSFET circuits
Power generation
Power MOSFET
Power MOSFET transistor
RESURF
Silicon on insulator technology
Silicon-on-Insulator
STI
Superjunction
Uniform resource locators
Uninterruptible power systems
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Beschreibung
Zusammenfassung:This paper is focused on the design and optimization of power LDMOS transistors with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 mum SOI-CMOS technology. Different LDMOS structures which allow breakdown voltages (V BR ) higher than 120 V have been analyzed by means of 2D and 3D TCAD simulations. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is compared in terms of the main static (specific on-state resistance vs breakdown voltage (R on-sp /V BR ) trade-off) and dynamic (Gate-to-Drain charge (Q gd ) and Gate charge (Q g ) vs R on trade-off) characteristics. The influence of some drift region design parameters, such as the Poly-gate (L Poly ) and STI (L STI ) lengths, are also exhaustively analyzed in this work.