Generating VHDL-A-like models using ABSynth
A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically transla...
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| creator | Moser, V. Amann, H.P. Nussbaum, P. Pellandini, F. |
| description | A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically translated into a VHDL-A-like analogue hardware description language. No syntax knowledge is necessary and the modelling time is reduced. |
| doi_str_mv | 10.1109/EURDAC.1995.527454 |
| format | Conference Proceeding |
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This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically translated into a VHDL-A-like analogue hardware description language. No syntax knowledge is necessary and the modelling time is reduced.</description><identifier>ISBN: 0818671564</identifier><identifier>ISBN: 9780818671562</identifier><identifier>DOI: 10.1109/EURDAC.1995.527454</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit simulation ; Code standards ; Electronic circuits ; Error correction codes ; Hardware design languages ; Iterative methods ; Libraries ; Packaging ; Standards development ; Synthesizers</subject><ispartof>Proceedings of EURO-DAC. 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European Design Automation Conference</title><addtitle>EURDAC</addtitle><description>A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically translated into a VHDL-A-like analogue hardware description language. No syntax knowledge is necessary and the modelling time is reduced.</description><subject>Circuit simulation</subject><subject>Code standards</subject><subject>Electronic circuits</subject><subject>Error correction codes</subject><subject>Hardware design languages</subject><subject>Iterative methods</subject><subject>Libraries</subject><subject>Packaging</subject><subject>Standards development</subject><subject>Synthesizers</subject><isbn>0818671564</isbn><isbn>9780818671562</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1995</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj0FLwzAYhgMiqNv-wE69S2q-5EuTHGs3N6EwUOd1JEui0a5KUw_7907mc3kOD7zwEjIHVgIwc7fcPi3qpgRjZCm5QokX5IZp0JUCWeEVmeX8wU6gBJD8mtyuQh8GO6b-rXhdL1pa0y59huLw5UOXi5_8F-r752M_vk_JZbRdDrN_T8j2YfnSrGm7WT02dUsToB5pVJX2wNBxzZnlSiLbWxW5M8IAWu-FcmA5gvFaVyehFCw6F9nec0AnJmR-3k0hhN33kA52OO7Od8Qvcf8-Nw</recordid><startdate>1995</startdate><enddate>1995</enddate><creator>Moser, V.</creator><creator>Amann, H.P.</creator><creator>Nussbaum, P.</creator><creator>Pellandini, F.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1995</creationdate><title>Generating VHDL-A-like models using ABSynth</title><author>Moser, V. ; Amann, H.P. ; Nussbaum, P. ; Pellandini, F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i148t-f768d104b2820a27540ca7f2b93914add37b1a2419d8864194530fbbf0cd214b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Circuit simulation</topic><topic>Code standards</topic><topic>Electronic circuits</topic><topic>Error correction codes</topic><topic>Hardware design languages</topic><topic>Iterative methods</topic><topic>Libraries</topic><topic>Packaging</topic><topic>Standards development</topic><topic>Synthesizers</topic><toplevel>online_resources</toplevel><creatorcontrib>Moser, V.</creatorcontrib><creatorcontrib>Amann, H.P.</creatorcontrib><creatorcontrib>Nussbaum, P.</creatorcontrib><creatorcontrib>Pellandini, F.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Moser, V.</au><au>Amann, H.P.</au><au>Nussbaum, P.</au><au>Pellandini, F.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Generating VHDL-A-like models using ABSynth</atitle><btitle>Proceedings of EURO-DAC. European Design Automation Conference</btitle><stitle>EURDAC</stitle><date>1995</date><risdate>1995</risdate><spage>522</spage><epage>527</epage><pages>522-527</pages><isbn>0818671564</isbn><isbn>9780818671562</isbn><abstract>A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically translated into a VHDL-A-like analogue hardware description language. No syntax knowledge is necessary and the modelling time is reduced.</abstract><pub>IEEE</pub><doi>10.1109/EURDAC.1995.527454</doi><tpages>6</tpages><oa>free_for_read</oa></addata></record> |
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| identifier | ISBN: 0818671564 |
| ispartof | Proceedings of EURO-DAC. European Design Automation Conference, 1995, p.522-527 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit simulation Code standards Electronic circuits Error correction codes Hardware design languages Iterative methods Libraries Packaging Standards development Synthesizers |
| title | Generating VHDL-A-like models using ABSynth |
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