Generating VHDL-A-like models using ABSynth

Generating VHDL-A-like models using ABSynth

A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically transla...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Moser, V., Amann, H.P., Nussbaum, P., Pellandini, F.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit simulation
Code standards
Electronic circuits
Error correction codes
Hardware design languages
Iterative methods
Libraries
Packaging
Standards development
Synthesizers
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Beschreibung
Zusammenfassung:A method for the graphical specification and the automatic generation of analogue behavioural models is presented. This method has been implemented as a new software tool called ABSynth. The behaviour of the component to model is described as a functional diagram, which is then automatically translated into a VHDL-A-like analogue hardware description language. No syntax knowledge is necessary and the modelling time is reduced.
DOI:10.1109/EURDAC.1995.527454