A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond
Results are presented for a fully planarized 0.25 /spl mu/m technology using a trench storage capacitor known as the "BEST" cell. In order to achieve a wide process window for fine patterning, a comprehensive global planarization scheme utilizing chemical mechanical polishing (CMP) is empl...
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| creator | Bronner, G. Aochi, H. Gall, M. Gambino, J. Gernhardt, S. Hammerl, E. Ho, H. Iba, J. Ishiuchi, H. Jaso, M. Kleinhenz, R. Mii, T. Narita, M. Nesbit, L. Neumueller, W. Nitayama, A. Ohiwa, T. Parke, S. Ryan, J. Sato, T. Takato, H. Yoshikawa, S. |
| description | Results are presented for a fully planarized 0.25 /spl mu/m technology using a trench storage capacitor known as the "BEST" cell. In order to achieve a wide process window for fine patterning, a comprehensive global planarization scheme utilizing chemical mechanical polishing (CMP) is employed. This scheme permits two levels of wiring at a minimum contacted pitch of 0.55 /spl mu/m and allows simplification of other processes related to the gate electrode and borderless array bitline contact. The technology has been exercised to fabricate a 256 Mb DRAM and is extendable to the 1 Gb generation by incremental technology scaling. |
| doi_str_mv | 10.1109/VLSIT.1995.520837 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_520837</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>520837</ieee_id><sourcerecordid>520837</sourcerecordid><originalsourceid>FETCH-ieee_primary_5208373</originalsourceid><addsrcrecordid>eNp9jssKgkAYRgciKMoHqNX_Auk403hZihUFWZDSVsYcyxgvzOjCnr6g1n0cOIuz-RBa2Ni0bexb12N8SEzb95nJCPaoO0KG73r4AyUOJs4EGVo_8Wdrxih1pugUQNFLOUArec1V-RI5YJMwsHQroeqtCsLoHEMnbo-6kc19gKJRQJgDUVZ2sLkEEfA6h0wMTZ3P0bjgUgvj5xla7rZJuF-VQoi0VWXF1ZB-z9G_8Q0Nejr9</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Bronner, G. ; Aochi, H. ; Gall, M. ; Gambino, J. ; Gernhardt, S. ; Hammerl, E. ; Ho, H. ; Iba, J. ; Ishiuchi, H. ; Jaso, M. ; Kleinhenz, R. ; Mii, T. ; Narita, M. ; Nesbit, L. ; Neumueller, W. ; Nitayama, A. ; Ohiwa, T. ; Parke, S. ; Ryan, J. ; Sato, T. ; Takato, H. ; Yoshikawa, S.</creator><creatorcontrib>Bronner, G. ; Aochi, H. ; Gall, M. ; Gambino, J. ; Gernhardt, S. ; Hammerl, E. ; Ho, H. ; Iba, J. ; Ishiuchi, H. ; Jaso, M. ; Kleinhenz, R. ; Mii, T. ; Narita, M. ; Nesbit, L. ; Neumueller, W. ; Nitayama, A. ; Ohiwa, T. ; Parke, S. ; Ryan, J. ; Sato, T. ; Takato, H. ; Yoshikawa, S.</creatorcontrib><description>Results are presented for a fully planarized 0.25 /spl mu/m technology using a trench storage capacitor known as the "BEST" cell. In order to achieve a wide process window for fine patterning, a comprehensive global planarization scheme utilizing chemical mechanical polishing (CMP) is employed. This scheme permits two levels of wiring at a minimum contacted pitch of 0.55 /spl mu/m and allows simplification of other processes related to the gate electrode and borderless array bitline contact. The technology has been exercised to fabricate a 256 Mb DRAM and is extendable to the 1 Gb generation by incremental technology scaling.</description><identifier>ISBN: 9780780326026</identifier><identifier>ISBN: 0780326024</identifier><identifier>DOI: 10.1109/VLSIT.1995.520837</identifier><language>eng</language><publisher>IEEE</publisher><subject>Aluminum ; Capacitors ; Chemical technology ; CMOS technology ; Electrodes ; Focusing ; Lithography ; Planarization ; Random access memory ; Wiring</subject><ispartof>1995 Symposium on VLSI Technology. Digest of Technical Papers, 1995, p.15-16</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/520837$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,4035,4036,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/520837$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bronner, G.</creatorcontrib><creatorcontrib>Aochi, H.</creatorcontrib><creatorcontrib>Gall, M.</creatorcontrib><creatorcontrib>Gambino, J.</creatorcontrib><creatorcontrib>Gernhardt, S.</creatorcontrib><creatorcontrib>Hammerl, E.</creatorcontrib><creatorcontrib>Ho, H.</creatorcontrib><creatorcontrib>Iba, J.</creatorcontrib><creatorcontrib>Ishiuchi, H.</creatorcontrib><creatorcontrib>Jaso, M.</creatorcontrib><creatorcontrib>Kleinhenz, R.</creatorcontrib><creatorcontrib>Mii, T.</creatorcontrib><creatorcontrib>Narita, M.</creatorcontrib><creatorcontrib>Nesbit, L.</creatorcontrib><creatorcontrib>Neumueller, W.</creatorcontrib><creatorcontrib>Nitayama, A.</creatorcontrib><creatorcontrib>Ohiwa, T.</creatorcontrib><creatorcontrib>Parke, S.</creatorcontrib><creatorcontrib>Ryan, J.</creatorcontrib><creatorcontrib>Sato, T.</creatorcontrib><creatorcontrib>Takato, H.</creatorcontrib><creatorcontrib>Yoshikawa, S.</creatorcontrib><title>A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond</title><title>1995 Symposium on VLSI Technology. Digest of Technical Papers</title><addtitle>VLSIT</addtitle><description>Results are presented for a fully planarized 0.25 /spl mu/m technology using a trench storage capacitor known as the "BEST" cell. In order to achieve a wide process window for fine patterning, a comprehensive global planarization scheme utilizing chemical mechanical polishing (CMP) is employed. This scheme permits two levels of wiring at a minimum contacted pitch of 0.55 /spl mu/m and allows simplification of other processes related to the gate electrode and borderless array bitline contact. The technology has been exercised to fabricate a 256 Mb DRAM and is extendable to the 1 Gb generation by incremental technology scaling.</description><subject>Aluminum</subject><subject>Capacitors</subject><subject>Chemical technology</subject><subject>CMOS technology</subject><subject>Electrodes</subject><subject>Focusing</subject><subject>Lithography</subject><subject>Planarization</subject><subject>Random access memory</subject><subject>Wiring</subject><isbn>9780780326026</isbn><isbn>0780326024</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1995</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jssKgkAYRgciKMoHqNX_Auk403hZihUFWZDSVsYcyxgvzOjCnr6g1n0cOIuz-RBa2Ni0bexb12N8SEzb95nJCPaoO0KG73r4AyUOJs4EGVo_8Wdrxih1pugUQNFLOUArec1V-RI5YJMwsHQroeqtCsLoHEMnbo-6kc19gKJRQJgDUVZ2sLkEEfA6h0wMTZ3P0bjgUgvj5xla7rZJuF-VQoi0VWXF1ZB-z9G_8Q0Nejr9</recordid><startdate>1995</startdate><enddate>1995</enddate><creator>Bronner, G.</creator><creator>Aochi, H.</creator><creator>Gall, M.</creator><creator>Gambino, J.</creator><creator>Gernhardt, S.</creator><creator>Hammerl, E.</creator><creator>Ho, H.</creator><creator>Iba, J.</creator><creator>Ishiuchi, H.</creator><creator>Jaso, M.</creator><creator>Kleinhenz, R.</creator><creator>Mii, T.</creator><creator>Narita, M.</creator><creator>Nesbit, L.</creator><creator>Neumueller, W.</creator><creator>Nitayama, A.</creator><creator>Ohiwa, T.</creator><creator>Parke, S.</creator><creator>Ryan, J.</creator><creator>Sato, T.</creator><creator>Takato, H.</creator><creator>Yoshikawa, S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1995</creationdate><title>A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond</title><author>Bronner, G. ; Aochi, H. ; Gall, M. ; Gambino, J. ; Gernhardt, S. ; Hammerl, E. ; Ho, H. ; Iba, J. ; Ishiuchi, H. ; Jaso, M. ; Kleinhenz, R. ; Mii, T. ; Narita, M. ; Nesbit, L. ; Neumueller, W. ; Nitayama, A. ; Ohiwa, T. ; Parke, S. ; Ryan, J. ; Sato, T. ; Takato, H. ; Yoshikawa, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_5208373</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Aluminum</topic><topic>Capacitors</topic><topic>Chemical technology</topic><topic>CMOS technology</topic><topic>Electrodes</topic><topic>Focusing</topic><topic>Lithography</topic><topic>Planarization</topic><topic>Random access memory</topic><topic>Wiring</topic><toplevel>online_resources</toplevel><creatorcontrib>Bronner, G.</creatorcontrib><creatorcontrib>Aochi, H.</creatorcontrib><creatorcontrib>Gall, M.</creatorcontrib><creatorcontrib>Gambino, J.</creatorcontrib><creatorcontrib>Gernhardt, S.</creatorcontrib><creatorcontrib>Hammerl, E.</creatorcontrib><creatorcontrib>Ho, H.</creatorcontrib><creatorcontrib>Iba, J.</creatorcontrib><creatorcontrib>Ishiuchi, H.</creatorcontrib><creatorcontrib>Jaso, M.</creatorcontrib><creatorcontrib>Kleinhenz, R.</creatorcontrib><creatorcontrib>Mii, T.</creatorcontrib><creatorcontrib>Narita, M.</creatorcontrib><creatorcontrib>Nesbit, L.</creatorcontrib><creatorcontrib>Neumueller, W.</creatorcontrib><creatorcontrib>Nitayama, A.</creatorcontrib><creatorcontrib>Ohiwa, T.</creatorcontrib><creatorcontrib>Parke, S.</creatorcontrib><creatorcontrib>Ryan, J.</creatorcontrib><creatorcontrib>Sato, T.</creatorcontrib><creatorcontrib>Takato, H.</creatorcontrib><creatorcontrib>Yoshikawa, S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bronner, G.</au><au>Aochi, H.</au><au>Gall, M.</au><au>Gambino, J.</au><au>Gernhardt, S.</au><au>Hammerl, E.</au><au>Ho, H.</au><au>Iba, J.</au><au>Ishiuchi, H.</au><au>Jaso, M.</au><au>Kleinhenz, R.</au><au>Mii, T.</au><au>Narita, M.</au><au>Nesbit, L.</au><au>Neumueller, W.</au><au>Nitayama, A.</au><au>Ohiwa, T.</au><au>Parke, S.</au><au>Ryan, J.</au><au>Sato, T.</au><au>Takato, H.</au><au>Yoshikawa, S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond</atitle><btitle>1995 Symposium on VLSI Technology. Digest of Technical Papers</btitle><stitle>VLSIT</stitle><date>1995</date><risdate>1995</risdate><spage>15</spage><epage>16</epage><pages>15-16</pages><isbn>9780780326026</isbn><isbn>0780326024</isbn><abstract>Results are presented for a fully planarized 0.25 /spl mu/m technology using a trench storage capacitor known as the "BEST" cell. In order to achieve a wide process window for fine patterning, a comprehensive global planarization scheme utilizing chemical mechanical polishing (CMP) is employed. This scheme permits two levels of wiring at a minimum contacted pitch of 0.55 /spl mu/m and allows simplification of other processes related to the gate electrode and borderless array bitline contact. The technology has been exercised to fabricate a 256 Mb DRAM and is extendable to the 1 Gb generation by incremental technology scaling.</abstract><pub>IEEE</pub><doi>10.1109/VLSIT.1995.520837</doi></addata></record> |
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| identifier | ISBN: 9780780326026 |
| ispartof | 1995 Symposium on VLSI Technology. Digest of Technical Papers, 1995, p.15-16 |
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| language | eng |
| recordid | cdi_ieee_primary_520837 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Aluminum Capacitors Chemical technology CMOS technology Electrodes Focusing Lithography Planarization Random access memory Wiring |
| title | A fully planarized 0.25 /spl mu/m CMOS technology for 256 Mbit DRAM and beyond |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-25T05%3A47%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20fully%20planarized%200.25%20/spl%20mu/m%20CMOS%20technology%20for%20256%20Mbit%20DRAM%20and%20beyond&rft.btitle=1995%20Symposium%20on%20VLSI%20Technology.%20Digest%20of%20Technical%20Papers&rft.au=Bronner,%20G.&rft.date=1995&rft.spage=15&rft.epage=16&rft.pages=15-16&rft.isbn=9780780326026&rft.isbn_list=0780326024&rft_id=info:doi/10.1109/VLSIT.1995.520837&rft_dat=%3Cieee_6IE%3E520837%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=520837&rfr_iscdi=true |