CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction

We demonstrate for the first time Schottky barrier height (SBH) tuning using interfacial SiO 2 /high-kappa dipoles resulting in SBH les 0.1 eV from the conduction band-edge (CBE) and SBH les 0.2 eV from the valence band-edge (VBE). The near band-edge electron and hole SBHs have been obtained using a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Coss, Brian E., Loh, Wei-Yip, Oh, Jungwoo, Smith, Greg, Smith, Casey, Adhikari, Hemant, Sassman, Barry, Parthasarathy, Srivatsan, Barnett, Joel, Majhi, Prashant, Wallace, Robert M., Kim, Jiyoung, Jammy, Raj
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 105
container_issue
container_start_page 104
container_title
container_volume
creator Coss, Brian E.
Loh, Wei-Yip
Oh, Jungwoo
Smith, Greg
Smith, Casey
Adhikari, Hemant
Sassman, Barry
Parthasarathy, Srivatsan
Barnett, Joel
Majhi, Prashant
Wallace, Robert M.
Kim, Jiyoung
Jammy, Raj
description We demonstrate for the first time Schottky barrier height (SBH) tuning using interfacial SiO 2 /high-kappa dipoles resulting in SBH les 0.1 eV from the conduction band-edge (CBE) and SBH les 0.2 eV from the valence band-edge (VBE). The near band-edge electron and hole SBHs have been obtained using a dielectric-dipole mitigated (DDM) scheme with single metal on Si junction. By optimizing the dielectric thickness, we obtained effective dipole modulation to the SBH of +0.5 and -0.3 eV for AlO x /SiO 2 and LaO x /SiO 2 , respectively, demonstrating reductions in SBH and contact resistance that are necessary for continued enhanced performance in future technology nodes.
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5200650</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5200650</ieee_id><sourcerecordid>5200650</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-6eef31687bb01dc8f9e89e8bd905b7b75dd9228dcf5e1d81b3bb3cbead3e40dd3</originalsourceid><addsrcrecordid>eNotjLtOwzAYRi2gEqH0CVg8wmDVlzhxRtRyk1p1aPfK9v8nNaRJZbsDL8BzUwmkTzpHZ_iuSCGFNqypjLwms6Y2opRlqRQ39Q0peF0qJnQlJ6RoOKu0FkrckruUPjmXXCtTkJ_FerOlzg7AEDqkyR_GnL--LynGgJEeMHSHnOg5haGjELBHn2PwDMJp7JEeQw6dzQj0cblcP9EjZtvPt4G2Y6RpPEePc4g2DNSPQ7Y-04gppGwHjxeFs89hHO7JpLV9wtk_p2T3-rJbvLPV5u1j8bxioeGZVYitEpWpneMCvGkbNJc5aLh2tas1QCOlAd9qFGCEU84p79CCwpIDqCl5-LsNiLg_xXC08XuvJeeV5uoXnYNisg</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Coss, Brian E. ; Loh, Wei-Yip ; Oh, Jungwoo ; Smith, Greg ; Smith, Casey ; Adhikari, Hemant ; Sassman, Barry ; Parthasarathy, Srivatsan ; Barnett, Joel ; Majhi, Prashant ; Wallace, Robert M. ; Kim, Jiyoung ; Jammy, Raj</creator><creatorcontrib>Coss, Brian E. ; Loh, Wei-Yip ; Oh, Jungwoo ; Smith, Greg ; Smith, Casey ; Adhikari, Hemant ; Sassman, Barry ; Parthasarathy, Srivatsan ; Barnett, Joel ; Majhi, Prashant ; Wallace, Robert M. ; Kim, Jiyoung ; Jammy, Raj</creatorcontrib><description>We demonstrate for the first time Schottky barrier height (SBH) tuning using interfacial SiO 2 /high-kappa dipoles resulting in SBH les 0.1 eV from the conduction band-edge (CBE) and SBH les 0.2 eV from the valence band-edge (VBE). The near band-edge electron and hole SBHs have been obtained using a dielectric-dipole mitigated (DDM) scheme with single metal on Si junction. By optimizing the dielectric thickness, we obtained effective dipole modulation to the SBH of +0.5 and -0.3 eV for AlO x /SiO 2 and LaO x /SiO 2 , respectively, demonstrating reductions in SBH and contact resistance that are necessary for continued enhanced performance in future technology nodes.</description><identifier>ISSN: 0743-1562</identifier><identifier>ISBN: 9781424433087</identifier><identifier>ISBN: 1424433088</identifier><identifier>EISSN: 2158-9682</identifier><identifier>LCCN: 90-655131</identifier><language>eng</language><publisher>IEEE</publisher><subject>Atherosclerosis ; Contact resistance ; Dielectric substrates ; dipoles ; Distributed decision making ; Electrical resistance measurement ; Electrons ; high-κ ; Schottky barrier height ; Schottky barriers ; Silicides ; Spectroscopy ; Thickness measurement</subject><ispartof>2009 Symposium on VLSI Technology, 2009, p.104-105</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5200650$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5200650$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Coss, Brian E.</creatorcontrib><creatorcontrib>Loh, Wei-Yip</creatorcontrib><creatorcontrib>Oh, Jungwoo</creatorcontrib><creatorcontrib>Smith, Greg</creatorcontrib><creatorcontrib>Smith, Casey</creatorcontrib><creatorcontrib>Adhikari, Hemant</creatorcontrib><creatorcontrib>Sassman, Barry</creatorcontrib><creatorcontrib>Parthasarathy, Srivatsan</creatorcontrib><creatorcontrib>Barnett, Joel</creatorcontrib><creatorcontrib>Majhi, Prashant</creatorcontrib><creatorcontrib>Wallace, Robert M.</creatorcontrib><creatorcontrib>Kim, Jiyoung</creatorcontrib><creatorcontrib>Jammy, Raj</creatorcontrib><title>CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction</title><title>2009 Symposium on VLSI Technology</title><addtitle>VLSIT</addtitle><description>We demonstrate for the first time Schottky barrier height (SBH) tuning using interfacial SiO 2 /high-kappa dipoles resulting in SBH les 0.1 eV from the conduction band-edge (CBE) and SBH les 0.2 eV from the valence band-edge (VBE). The near band-edge electron and hole SBHs have been obtained using a dielectric-dipole mitigated (DDM) scheme with single metal on Si junction. By optimizing the dielectric thickness, we obtained effective dipole modulation to the SBH of +0.5 and -0.3 eV for AlO x /SiO 2 and LaO x /SiO 2 , respectively, demonstrating reductions in SBH and contact resistance that are necessary for continued enhanced performance in future technology nodes.</description><subject>Atherosclerosis</subject><subject>Contact resistance</subject><subject>Dielectric substrates</subject><subject>dipoles</subject><subject>Distributed decision making</subject><subject>Electrical resistance measurement</subject><subject>Electrons</subject><subject>high-κ</subject><subject>Schottky barrier height</subject><subject>Schottky barriers</subject><subject>Silicides</subject><subject>Spectroscopy</subject><subject>Thickness measurement</subject><issn>0743-1562</issn><issn>2158-9682</issn><isbn>9781424433087</isbn><isbn>1424433088</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjLtOwzAYRi2gEqH0CVg8wmDVlzhxRtRyk1p1aPfK9v8nNaRJZbsDL8BzUwmkTzpHZ_iuSCGFNqypjLwms6Y2opRlqRQ39Q0peF0qJnQlJ6RoOKu0FkrckruUPjmXXCtTkJ_FerOlzg7AEDqkyR_GnL--LynGgJEeMHSHnOg5haGjELBHn2PwDMJp7JEeQw6dzQj0cblcP9EjZtvPt4G2Y6RpPEePc4g2DNSPQ7Y-04gppGwHjxeFs89hHO7JpLV9wtk_p2T3-rJbvLPV5u1j8bxioeGZVYitEpWpneMCvGkbNJc5aLh2tas1QCOlAd9qFGCEU84p79CCwpIDqCl5-LsNiLg_xXC08XuvJeeV5uoXnYNisg</recordid><startdate>200906</startdate><enddate>200906</enddate><creator>Coss, Brian E.</creator><creator>Loh, Wei-Yip</creator><creator>Oh, Jungwoo</creator><creator>Smith, Greg</creator><creator>Smith, Casey</creator><creator>Adhikari, Hemant</creator><creator>Sassman, Barry</creator><creator>Parthasarathy, Srivatsan</creator><creator>Barnett, Joel</creator><creator>Majhi, Prashant</creator><creator>Wallace, Robert M.</creator><creator>Kim, Jiyoung</creator><creator>Jammy, Raj</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200906</creationdate><title>CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction</title><author>Coss, Brian E. ; Loh, Wei-Yip ; Oh, Jungwoo ; Smith, Greg ; Smith, Casey ; Adhikari, Hemant ; Sassman, Barry ; Parthasarathy, Srivatsan ; Barnett, Joel ; Majhi, Prashant ; Wallace, Robert M. ; Kim, Jiyoung ; Jammy, Raj</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-6eef31687bb01dc8f9e89e8bd905b7b75dd9228dcf5e1d81b3bb3cbead3e40dd3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Atherosclerosis</topic><topic>Contact resistance</topic><topic>Dielectric substrates</topic><topic>dipoles</topic><topic>Distributed decision making</topic><topic>Electrical resistance measurement</topic><topic>Electrons</topic><topic>high-κ</topic><topic>Schottky barrier height</topic><topic>Schottky barriers</topic><topic>Silicides</topic><topic>Spectroscopy</topic><topic>Thickness measurement</topic><toplevel>online_resources</toplevel><creatorcontrib>Coss, Brian E.</creatorcontrib><creatorcontrib>Loh, Wei-Yip</creatorcontrib><creatorcontrib>Oh, Jungwoo</creatorcontrib><creatorcontrib>Smith, Greg</creatorcontrib><creatorcontrib>Smith, Casey</creatorcontrib><creatorcontrib>Adhikari, Hemant</creatorcontrib><creatorcontrib>Sassman, Barry</creatorcontrib><creatorcontrib>Parthasarathy, Srivatsan</creatorcontrib><creatorcontrib>Barnett, Joel</creatorcontrib><creatorcontrib>Majhi, Prashant</creatorcontrib><creatorcontrib>Wallace, Robert M.</creatorcontrib><creatorcontrib>Kim, Jiyoung</creatorcontrib><creatorcontrib>Jammy, Raj</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Coss, Brian E.</au><au>Loh, Wei-Yip</au><au>Oh, Jungwoo</au><au>Smith, Greg</au><au>Smith, Casey</au><au>Adhikari, Hemant</au><au>Sassman, Barry</au><au>Parthasarathy, Srivatsan</au><au>Barnett, Joel</au><au>Majhi, Prashant</au><au>Wallace, Robert M.</au><au>Kim, Jiyoung</au><au>Jammy, Raj</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction</atitle><btitle>2009 Symposium on VLSI Technology</btitle><stitle>VLSIT</stitle><date>2009-06</date><risdate>2009</risdate><spage>104</spage><epage>105</epage><pages>104-105</pages><issn>0743-1562</issn><eissn>2158-9682</eissn><isbn>9781424433087</isbn><isbn>1424433088</isbn><abstract>We demonstrate for the first time Schottky barrier height (SBH) tuning using interfacial SiO 2 /high-kappa dipoles resulting in SBH les 0.1 eV from the conduction band-edge (CBE) and SBH les 0.2 eV from the valence band-edge (VBE). The near band-edge electron and hole SBHs have been obtained using a dielectric-dipole mitigated (DDM) scheme with single metal on Si junction. By optimizing the dielectric thickness, we obtained effective dipole modulation to the SBH of +0.5 and -0.3 eV for AlO x /SiO 2 and LaO x /SiO 2 , respectively, demonstrating reductions in SBH and contact resistance that are necessary for continued enhanced performance in future technology nodes.</abstract><pub>IEEE</pub><tpages>2</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0743-1562
ispartof 2009 Symposium on VLSI Technology, 2009, p.104-105
issn 0743-1562
2158-9682
language eng
recordid cdi_ieee_primary_5200650
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Atherosclerosis
Contact resistance
Dielectric substrates
dipoles
Distributed decision making
Electrical resistance measurement
Electrons
high-κ
Schottky barrier height
Schottky barriers
Silicides
Spectroscopy
Thickness measurement
title CMOS band-edge schottky barrier heights using dielectric-dipole mitigated (DDM) metal/Si for source/drain contact resistance reduction
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-18T23%3A06%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=CMOS%20band-edge%20schottky%20barrier%20heights%20using%20dielectric-dipole%20mitigated%20(DDM)%20metal/Si%20for%20source/drain%20contact%20resistance%20reduction&rft.btitle=2009%20Symposium%20on%20VLSI%20Technology&rft.au=Coss,%20Brian%20E.&rft.date=2009-06&rft.spage=104&rft.epage=105&rft.pages=104-105&rft.issn=0743-1562&rft.eissn=2158-9682&rft.isbn=9781424433087&rft.isbn_list=1424433088&rft_id=info:doi/&rft_dat=%3Cieee_6IE%3E5200650%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5200650&rfr_iscdi=true