Architecture tradeoffs in in reduced instruction set computers: a case study

A major problem facing computer architects is the development of methods and techniques that measure and predict the performance of their architectures. This problem arises also in designing reduced instruction set computers (RISCs). The paper studies the effect of machine instruction set on performance of a subset of RISC architectures. In particular, the study investigates the behavior and performance issues of a minimal VLSI-estate RISC architecture (LDS RISC) designed by the Lambda Digital Synthesis Group in the Department of Computational Science, University of Saskatchewan. The authors address issues in architectural design. Such as register-to-memory architecture versus load/store, instruction frequency distribution, and suitability for pipelining as they apply to the LDS architecture. An instruction simulator and profiler are written for the LDS architecture. Performance statistics are gathered during the run-time of a benchmark suite on the LDS architecture. The authors anticipate that the gathered measurements serve as the knowledge base that can be used by an architect in making detailed design tradeoffs to achieve a better architecture. The proposed modifications aim for less memory references, and faster speed than the original LDS architecture.