Testability analysis of multichip systems

This paper describes a tool that aids the designer in identifying test bottlenecks in the design and evaluating potential solutions. The input to the tool is a circuit description that includes the chips used and their characteristics, the relation between major input and output ports on the chip, and the connectivity information between the chips. The tool analyzes the information and computes testability figure of merits for all parts of the design. These numbers are used to characterize the testability impact of various Design for Test (DFT) solutions and to understand the global effects of local DFT changes. The paper also outlines various applications of the tool.