A middleware aided robust and fault tolerant dynamic reconfigurable architecture

Dynamic reconfiguration enhances embedded system with at run-time adaptive functionality and is an improvement in terms of resource utilization and system adaptability. SRAM-based FPGAs provides a dynamic reconfigurable platform with high logic density. The requirements for such an embedded high fle...

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Bibliographische Detailangaben
Hauptverfasser:	Dadji, Y., Osterloh, B., Michalik, H.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application software Embedded system Fault tolerance Field programmable gate arrays FPGA Middleware Network-on-a-chip Network-on-Chip Reconfigurable architectures Reconfigurable logic Resource management Robustness SoCWire Virtex
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Beschreibung
Zusammenfassung:	Dynamic reconfiguration enhances embedded system with at run-time adaptive functionality and is an improvement in terms of resource utilization and system adaptability. SRAM-based FPGAs provides a dynamic reconfigurable platform with high logic density. The requirements for such an embedded high flexible system based on FPGAs are robustness and reliability to prevent operation interrupts or even system failures. The complexity of a dynamic reconfigurable system with adaptive processing module demands high effort for the user. Therefore a high level abstraction of the communication issues is required to support application development by an appropriate middleware. To achieve such a flexible embedded system we present our network-on-chip (NoC) approach system-on-chip wire (SoCWire) and outline its performance and suitability for robust dynamic reconfigurable systems. Furthermore we introduce a suitable embedded middleware concept to support the system reconfiguration and the software application development process.