Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116 nA at 25degC, which is much smaller than that (613 muA) of traditional design. Moreover, it can achieve ESD robustness of over 8 kV in HBM and 800 V i...

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Bibliographische Detailangaben
Hauptverfasser: Po-Yen Chiu, Ming-Dou Ker, Fu-Yi Tsai, Yeong-Jar Chang
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Clamps
CMOS process
CMOS technology
Electrostatic discharge
electrostatic discharge (ESD)
ESD clamp circuit
Gate leakage
Leak detection
Leakage current
MOS capacitors
silicon-controlled rectifier (SCR)
Thyristors
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Beschreibung
Zusammenfassung:A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116 nA at 25degC, which is much smaller than that (613 muA) of traditional design. Moreover, it can achieve ESD robustness of over 8 kV in HBM and 800 V in MM ESD tests, respectively.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2009.5173343