A fast recorder for changes of a resistance during joint failure in electronics

A main goal for this publication is a demonstration of a device and an algorithm designed for thorough examination of resistance changes of joints during accelerated tests. Even during accelerated tests it takes long time to observe failure of the joint-up to couple of weeks. However, it is important to measure resistance changes using high frequencies (up to 100 MSPS). It is also important to build a systems which measures many channels simultaneously. In practice, it is impossible to use general-purpose data acquisition devices due to very high amounts of data produced (up to 200 MB/s for single channel, which is over 15 TB per day). It is also difficult to implement user-defined algorithms for on-board event detection using such devices. A solution proposed in this paper is the FPGA-based device with user definable event detector VHDL algorithm. An FPGA together with fast ADC continuously acquires the data and stores it in internal memory in cyclic buffers. After failure detection the content of the buffer is send to the PC for further analysis. Such events occur rarely-in fact, when a permanent failure occurs, it is just single data packet. Such packet contains a values of resistance just before, during and after joint crack.