Experimental Demonstration of Concatenated LDPC and RS Codes by FPGAs Emulation

The concatenation of low-density parity-check and Reed-Solomon codes for forward error correction has been experimentally demonstrated for the first time in this letter. Using a 2-bit soft-decision large-scale integration and high-speed field-programmable gate arrays, a net coding gain of 9.0 dB was...

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Veröffentlicht in:	IEEE photonics technology letters 2009-09, Vol.21 (18), p.1302-1304
Hauptverfasser:	Mizuochi, T., Konishi, Y., Miyata, Y., Inoue, T., Onohara, K., Kametani, S., Sugihara, T., Kubo, K., Yoshida, H., Kobayashi, T., Ichikawa, T.
Format:	Artikel
Sprache:	eng
Schlagworte:	Coding Concatenated codes Concatenated coding Decoding Emulation Field programmable gate arrays field-programmable gate arrays (FPGAs) Forward error correction forward error correction (FEC) Gain Gate arrays High speed Iterative decoding Large scale integration Noise levels optical communication Parity check codes Photonics Redundancy Reed-Solomon (RS) codes Reed-Solomon codes
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Zusammenfassung:	The concatenation of low-density parity-check and Reed-Solomon codes for forward error correction has been experimentally demonstrated for the first time in this letter. Using a 2-bit soft-decision large-scale integration and high-speed field-programmable gate arrays, a net coding gain of 9.0 dB was achieved with 20.5% redundancy with four iterative decoding for an input bit-error rate of 8.9 times 10 -3 at 31.3 Gb/s.
ISSN:	1041-1135 1941-0174
DOI:	10.1109/LPT.2009.2025867