aBCD18 - An advanced 0.18um BCD technology for PMIC application

aBCD18 - An advanced 0.18um BCD technology for PMIC application

We present a new advanced 0.18 um BCD(Bipolar-CMOS-DMOS) technology with the key features being a 40 V HV-MOS and an SSTC(Sidewall Selective Transistor Cell) type EEPROM as well as complimentary available analog devices such as a high gain BJT, 4fF/um 2 MIM capacitor, and 10k Omega/sq. poly resistor...

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Hauptverfasser: Namkyu Park, Jaehan Cha, Kyungho Lee, Haeung Jeon, Hyungsuk Choi, Juho Kim, Sungoo Kim, Inseok Oh, Eungryul Park, Jinyoung Chae, Hyunggeun Kang, Intaek Oh, Han Sub Yoon
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Auditory displays
Diffusion tensor imaging
EPROM
Isolation technology
Logic devices
Metal-insulator structures
MIM capacitors
Nonvolatile memory
Resistors
Voltage
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Beschreibung
Zusammenfassung:We present a new advanced 0.18 um BCD(Bipolar-CMOS-DMOS) technology with the key features being a 40 V HV-MOS and an SSTC(Sidewall Selective Transistor Cell) type EEPROM as well as complimentary available analog devices such as a high gain BJT, 4fF/um 2 MIM capacitor, and 10k Omega/sq. poly resistor. To reduce device area and enhance latch up immunity, a 15 um depth deep trench isolation process has been developed, which will help to significantly reduce the chip size.
ISSN:1063-6854
1946-0201
DOI:10.1109/ISPSD.2009.5158044