Dynamically reconfigurable VLD circuit

Dynamically reconfigurable VLD circuit

A dynamically reconfigurable VLD (variable length decode) circuit is proposed. In this circuit, several comparators decode at input bitstream in parallel. Furthermore it can also decode next code in same time, using some comparators. The rate of number of comparators used for parallel and next code...

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Bibliographische Detailangaben
Hauptverfasser: Komoku, K., Miyake, T., Morishita, T., Sasaki, N.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Consumer electronics
Data compression
Decoding
Detectors
Digital audio players
Encoding
Energy consumption
reconfigurable
Statistics
Throughput
variavle length decode
VLD
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Beschreibung
Zusammenfassung:A dynamically reconfigurable VLD (variable length decode) circuit is proposed. In this circuit, several comparators decode at input bitstream in parallel. Furthermore it can also decode next code in same time, using some comparators. The rate of number of comparators used for parallel and next code decoding is variable and the reconfiguration can be executed dynamically.
ISSN:0747-668X
2159-1423
DOI:10.1109/ISCE.2009.5157031