An investigation of the chemical mechanical polishing of copper thin films to form in-laid interconnections in the dielectric (SiO/sub 2/) films

Summary form only given. Describes an investigation of the chemical mechanical polishing (CMP) of copper films for the purpose of delineating and planarizing inlaid copper interconnections for multilevel metallization in silicon integrated circuits. Copper CMP has been shown to be an effective method of patterning interconnections and for providing the global planarity required to build multilevel structures. CMP processes in general, however, remain poorly understood and unoptimized. The task of optimizing a process is hampered by the lack of a fundamental understanding of the removal mechanisms at work in CMP. A fundamental understanding of these mechanisms will allow greater control of the CMP process in the manufacturing environment.