Behavior to structure: using Verilog and in-circuit emulation to teach how an algorithm becomes hardware

We present three stages of Verilog simulation (pure behavioral, mixed behavioral/structural, and pure structural), and a final stage of in-circuit emulation for translating an algorithm into hardware. Each successive stage in the translation can be derived by minor editing of the previous stage. The pure behavioral stage uses a single Verilog process to model an algorithmic state machine (ASM) using statements such as while and non-blocking assignment. The mixed stage keeps the algorithm in a readable form using statements such as while, but replaces the non-blocking assignment with a structural "architecture" that manipulates data. The third stage replaces statements such as while with a simulation of a conventional structural controller that generates the next state. The final stage involves synthesizing actual hardware for the controller, and interfacing it to the Verilog simulation of the architecture using an MS-DOS device driver that works in cooperation with a special module in VeriWell/PC.