Novel low voltage current-mirror sense amplifier based Flip-Flop with reduced delay time
A new current-mirror sense-amplifier based flip-flop (CMSA-FF) for ultra-low voltage applications is presented in this paper. The better performance of the proposed flip-flop at ultra-low voltage (down to 120 mV) can be achieved by reducing the number of stacked transistors from VDD to GND compared...
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creator | Tuan Vu Cao Wisland, D.T. Moradi, F. Lande, T.S. |
description | A new current-mirror sense-amplifier based flip-flop (CMSA-FF) for ultra-low voltage applications is presented in this paper. The better performance of the proposed flip-flop at ultra-low voltage (down to 120 mV) can be achieved by reducing the number of stacked transistors from VDD to GND compared to conventional SAFFs. The speed improvement of CMSA-FF is also obtained by reducing the discharging time and the setup time/hold time of the pulse generator stage as well as the delay of the set-reset (SR) latch stage. This reduces the clock to output delay time of the CMSA-FF by 56.94 %, and the setup/hold time window smaller and closer to the clock trigger edge. The proposed flip-flop is implemented in a 65 nm CMOS technology. |
doi_str_mv | 10.1109/ISCAS.2009.5118475 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5118475</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5118475</ieee_id><sourcerecordid>5118475</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-dc7cd2c92b5b74e6bb54526db4f314541b2949dd49f1d6c7ad2fabc8aae378953</originalsourceid><addsrcrecordid>eNpFkMtKAzEYRuOl4LT6ArrJC6QmmVyXpVgtFF1UwV1JJv9oJNMZMtOWvr0FC64-OAfO4kPontEpY9Q-Ltfz2XrKKbVTyZgRWl6gMRNciNJwIy5RwZk0hEkur_6FVteooFwzIkrKR6gwlCihZElv0Ljvfyg9FRUv0Odru4eEU3vA-zYN7gtwtcsZtgNpYs5txj1se8Cu6VKsI2TsXQ8BL1LsyCK1HT7E4RtnCLvqhAMkd8RDbOAWjWqXerg77wR9LJ7e5y9k9fa8nM9WJDItBxIqXQVeWe6l1wKU91JIroIXdcmEFMxzK2wIwtYsqEq7wGvnK-MclNpYWU7Qw183AsCmy7Fx-bg5X1X-AmppWI8</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Novel low voltage current-mirror sense amplifier based Flip-Flop with reduced delay time</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Tuan Vu Cao ; Wisland, D.T. ; Moradi, F. ; Lande, T.S.</creator><creatorcontrib>Tuan Vu Cao ; Wisland, D.T. ; Moradi, F. ; Lande, T.S.</creatorcontrib><description>A new current-mirror sense-amplifier based flip-flop (CMSA-FF) for ultra-low voltage applications is presented in this paper. The better performance of the proposed flip-flop at ultra-low voltage (down to 120 mV) can be achieved by reducing the number of stacked transistors from VDD to GND compared to conventional SAFFs. The speed improvement of CMSA-FF is also obtained by reducing the discharging time and the setup time/hold time of the pulse generator stage as well as the delay of the set-reset (SR) latch stage. This reduces the clock to output delay time of the CMSA-FF by 56.94 %, and the setup/hold time window smaller and closer to the clock trigger edge. The proposed flip-flop is implemented in a 65 nm CMOS technology.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 1424438276</identifier><identifier>ISBN: 9781424438273</identifier><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 1424438284</identifier><identifier>EISBN: 9781424438280</identifier><identifier>DOI: 10.1109/ISCAS.2009.5118475</identifier><identifier>LCCN: 80-646530</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuits ; Clocks ; CMOS technology ; Delay effects ; Flip-flops ; Frequency ; Low voltage ; Metastasis ; Propagation delay ; Timing</subject><ispartof>2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.3166-3169</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5118475$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5118475$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Tuan Vu Cao</creatorcontrib><creatorcontrib>Wisland, D.T.</creatorcontrib><creatorcontrib>Moradi, F.</creatorcontrib><creatorcontrib>Lande, T.S.</creatorcontrib><title>Novel low voltage current-mirror sense amplifier based Flip-Flop with reduced delay time</title><title>2009 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>A new current-mirror sense-amplifier based flip-flop (CMSA-FF) for ultra-low voltage applications is presented in this paper. The better performance of the proposed flip-flop at ultra-low voltage (down to 120 mV) can be achieved by reducing the number of stacked transistors from VDD to GND compared to conventional SAFFs. The speed improvement of CMSA-FF is also obtained by reducing the discharging time and the setup time/hold time of the pulse generator stage as well as the delay of the set-reset (SR) latch stage. This reduces the clock to output delay time of the CMSA-FF by 56.94 %, and the setup/hold time window smaller and closer to the clock trigger edge. The proposed flip-flop is implemented in a 65 nm CMOS technology.</description><subject>Circuits</subject><subject>Clocks</subject><subject>CMOS technology</subject><subject>Delay effects</subject><subject>Flip-flops</subject><subject>Frequency</subject><subject>Low voltage</subject><subject>Metastasis</subject><subject>Propagation delay</subject><subject>Timing</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>1424438276</isbn><isbn>9781424438273</isbn><isbn>1424438284</isbn><isbn>9781424438280</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkMtKAzEYRuOl4LT6ArrJC6QmmVyXpVgtFF1UwV1JJv9oJNMZMtOWvr0FC64-OAfO4kPontEpY9Q-Ltfz2XrKKbVTyZgRWl6gMRNciNJwIy5RwZk0hEkur_6FVteooFwzIkrKR6gwlCihZElv0Ljvfyg9FRUv0Odru4eEU3vA-zYN7gtwtcsZtgNpYs5txj1se8Cu6VKsI2TsXQ8BL1LsyCK1HT7E4RtnCLvqhAMkd8RDbOAWjWqXerg77wR9LJ7e5y9k9fa8nM9WJDItBxIqXQVeWe6l1wKU91JIroIXdcmEFMxzK2wIwtYsqEq7wGvnK-MclNpYWU7Qw183AsCmy7Fx-bg5X1X-AmppWI8</recordid><startdate>200905</startdate><enddate>200905</enddate><creator>Tuan Vu Cao</creator><creator>Wisland, D.T.</creator><creator>Moradi, F.</creator><creator>Lande, T.S.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200905</creationdate><title>Novel low voltage current-mirror sense amplifier based Flip-Flop with reduced delay time</title><author>Tuan Vu Cao ; Wisland, D.T. ; Moradi, F. ; Lande, T.S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-dc7cd2c92b5b74e6bb54526db4f314541b2949dd49f1d6c7ad2fabc8aae378953</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Circuits</topic><topic>Clocks</topic><topic>CMOS technology</topic><topic>Delay effects</topic><topic>Flip-flops</topic><topic>Frequency</topic><topic>Low voltage</topic><topic>Metastasis</topic><topic>Propagation delay</topic><topic>Timing</topic><toplevel>online_resources</toplevel><creatorcontrib>Tuan Vu Cao</creatorcontrib><creatorcontrib>Wisland, D.T.</creatorcontrib><creatorcontrib>Moradi, F.</creatorcontrib><creatorcontrib>Lande, T.S.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tuan Vu Cao</au><au>Wisland, D.T.</au><au>Moradi, F.</au><au>Lande, T.S.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Novel low voltage current-mirror sense amplifier based Flip-Flop with reduced delay time</atitle><btitle>2009 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2009-05</date><risdate>2009</risdate><spage>3166</spage><epage>3169</epage><pages>3166-3169</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>1424438276</isbn><isbn>9781424438273</isbn><eisbn>1424438284</eisbn><eisbn>9781424438280</eisbn><abstract>A new current-mirror sense-amplifier based flip-flop (CMSA-FF) for ultra-low voltage applications is presented in this paper. The better performance of the proposed flip-flop at ultra-low voltage (down to 120 mV) can be achieved by reducing the number of stacked transistors from VDD to GND compared to conventional SAFFs. The speed improvement of CMSA-FF is also obtained by reducing the discharging time and the setup time/hold time of the pulse generator stage as well as the delay of the set-reset (SR) latch stage. This reduces the clock to output delay time of the CMSA-FF by 56.94 %, and the setup/hold time window smaller and closer to the clock trigger edge. The proposed flip-flop is implemented in a 65 nm CMOS technology.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2009.5118475</doi><tpages>4</tpages></addata></record> |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Circuits Clocks CMOS technology Delay effects Flip-flops Frequency Low voltage Metastasis Propagation delay Timing |
title | Novel low voltage current-mirror sense amplifier based Flip-Flop with reduced delay time |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T14%3A56%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Novel%20low%20voltage%20current-mirror%20sense%20amplifier%20based%20Flip-Flop%20with%20reduced%20delay%20time&rft.btitle=2009%20IEEE%20International%20Symposium%20on%20Circuits%20and%20Systems%20(ISCAS)&rft.au=Tuan%20Vu%20Cao&rft.date=2009-05&rft.spage=3166&rft.epage=3169&rft.pages=3166-3169&rft.issn=0271-4302&rft.eissn=2158-1525&rft.isbn=1424438276&rft.isbn_list=9781424438273&rft_id=info:doi/10.1109/ISCAS.2009.5118475&rft_dat=%3Cieee_6IE%3E5118475%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=1424438284&rft.eisbn_list=9781424438280&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5118475&rfr_iscdi=true |