Novel low voltage current-mirror sense amplifier based Flip-Flop with reduced delay time

A new current-mirror sense-amplifier based flip-flop (CMSA-FF) for ultra-low voltage applications is presented in this paper. The better performance of the proposed flip-flop at ultra-low voltage (down to 120 mV) can be achieved by reducing the number of stacked transistors from VDD to GND compared to conventional SAFFs. The speed improvement of CMSA-FF is also obtained by reducing the discharging time and the setup time/hold time of the pulse generator stage as well as the delay of the set-reset (SR) latch stage. This reduces the clock to output delay time of the CMSA-FF by 56.94 %, and the setup/hold time window smaller and closer to the clock trigger edge. The proposed flip-flop is implemented in a 65 nm CMOS technology.