High voltage tolerant integrated Buck converter in 65nm 2.5V CMOS
In this paper, an integrated DC-DC (Buck) converter is presented. The Buck converter accepts input voltage in the range 2.7-5.5 V while using 2.5 V devices. A low drop-out (LDO) regulator is used to limit the maximum input voltage to the DCDC switches to protect it against overvoltage breakdown. 5 M...
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creator | Emira, A. Carr, F. Elwan, H. Mekky, R.H. |
description | In this paper, an integrated DC-DC (Buck) converter is presented. The Buck converter accepts input voltage in the range 2.7-5.5 V while using 2.5 V devices. A low drop-out (LDO) regulator is used to limit the maximum input voltage to the DCDC switches to protect it against overvoltage breakdown. 5 MHz switching frequency is used to allow using smaller external inductors. The Buck converter is implemented in TSMC 65 nm CMOS technology and it occupies 0.15 mm 2 while the LDO regulator, bandgap, clock generator and bias circuits occupy 0.19 mm 2 . Up to 88% and 77% efficiency is achieved at 2.5 V and 1.2 V output, respectively, using 3.6 V input. If the input voltage is limited to 3.3 V, the LDO regulator is bypassed, and the peak efficiency becomes 92% for 2.5 V and 85% for 1.2 V output. |
doi_str_mv | 10.1109/ISCAS.2009.5118285 |
format | Conference Proceeding |
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The Buck converter accepts input voltage in the range 2.7-5.5 V while using 2.5 V devices. A low drop-out (LDO) regulator is used to limit the maximum input voltage to the DCDC switches to protect it against overvoltage breakdown. 5 MHz switching frequency is used to allow using smaller external inductors. The Buck converter is implemented in TSMC 65 nm CMOS technology and it occupies 0.15 mm 2 while the LDO regulator, bandgap, clock generator and bias circuits occupy 0.19 mm 2 . Up to 88% and 77% efficiency is achieved at 2.5 V and 1.2 V output, respectively, using 3.6 V input. If the input voltage is limited to 3.3 V, the LDO regulator is bypassed, and the peak efficiency becomes 92% for 2.5 V and 85% for 1.2 V output.</description><identifier>ISSN: 0271-4302</identifier><identifier>ISBN: 1424438276</identifier><identifier>ISBN: 9781424438273</identifier><identifier>EISSN: 2158-1525</identifier><identifier>EISBN: 1424438284</identifier><identifier>EISBN: 9781424438280</identifier><identifier>DOI: 10.1109/ISCAS.2009.5118285</identifier><identifier>LCCN: 80-646530</identifier><language>eng</language><publisher>IEEE</publisher><subject>Breakdown voltage ; Buck converters ; CMOS technology ; DC-DC power converters ; Inductors ; Protection ; Regulators ; Switches ; Switching frequency ; Voltage control</subject><ispartof>2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.2405-2408</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5118285$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5118285$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Emira, A.</creatorcontrib><creatorcontrib>Carr, F.</creatorcontrib><creatorcontrib>Elwan, H.</creatorcontrib><creatorcontrib>Mekky, R.H.</creatorcontrib><title>High voltage tolerant integrated Buck converter in 65nm 2.5V CMOS</title><title>2009 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>In this paper, an integrated DC-DC (Buck) converter is presented. The Buck converter accepts input voltage in the range 2.7-5.5 V while using 2.5 V devices. A low drop-out (LDO) regulator is used to limit the maximum input voltage to the DCDC switches to protect it against overvoltage breakdown. 5 MHz switching frequency is used to allow using smaller external inductors. The Buck converter is implemented in TSMC 65 nm CMOS technology and it occupies 0.15 mm 2 while the LDO regulator, bandgap, clock generator and bias circuits occupy 0.19 mm 2 . Up to 88% and 77% efficiency is achieved at 2.5 V and 1.2 V output, respectively, using 3.6 V input. If the input voltage is limited to 3.3 V, the LDO regulator is bypassed, and the peak efficiency becomes 92% for 2.5 V and 85% for 1.2 V output.</description><subject>Breakdown voltage</subject><subject>Buck converters</subject><subject>CMOS technology</subject><subject>DC-DC power converters</subject><subject>Inductors</subject><subject>Protection</subject><subject>Regulators</subject><subject>Switches</subject><subject>Switching frequency</subject><subject>Voltage control</subject><issn>0271-4302</issn><issn>2158-1525</issn><isbn>1424438276</isbn><isbn>9781424438273</isbn><isbn>1424438284</isbn><isbn>9781424438280</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2009</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFkM1Kw0AUhcefgmn1BXQzL5A4985PZpY1VFuodFF1W2aS2xhNU0nHgm9vwIKrw-GDj8Nh7BZEBiDc_WJdTNcZCuEyDWDR6jM2BoVKyaGoc5YgaJuCRn3xD3JzyRKBOaRKChyxxIrUKKOluGLjw-FDiMFoMGHTeVO_8-O-jb4mHvct9b6LvOki1b2PVPGH7_KTl_vuSH2kfiDc6G7HMdNvvHhera_ZaOvbA92ccsJeH2cvxTxdrp4WxXSZNpDrmOY-DKsIyBqFDkuvdV4JK0up0RkoqyBdqIJRTm5lFRACYV4G4QIp79HKCbv78zZEtPnqm53vfzanT-QveaZNqQ</recordid><startdate>200905</startdate><enddate>200905</enddate><creator>Emira, A.</creator><creator>Carr, F.</creator><creator>Elwan, H.</creator><creator>Mekky, R.H.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200905</creationdate><title>High voltage tolerant integrated Buck converter in 65nm 2.5V CMOS</title><author>Emira, A. ; Carr, F. ; Elwan, H. ; Mekky, R.H.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-7ab276e1e864292ca557d083c352961cdb39bdb6493f3db21be27cb09be4aa283</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2009</creationdate><topic>Breakdown voltage</topic><topic>Buck converters</topic><topic>CMOS technology</topic><topic>DC-DC power converters</topic><topic>Inductors</topic><topic>Protection</topic><topic>Regulators</topic><topic>Switches</topic><topic>Switching frequency</topic><topic>Voltage control</topic><toplevel>online_resources</toplevel><creatorcontrib>Emira, A.</creatorcontrib><creatorcontrib>Carr, F.</creatorcontrib><creatorcontrib>Elwan, H.</creatorcontrib><creatorcontrib>Mekky, R.H.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Emira, A.</au><au>Carr, F.</au><au>Elwan, H.</au><au>Mekky, R.H.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High voltage tolerant integrated Buck converter in 65nm 2.5V CMOS</atitle><btitle>2009 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>2009-05</date><risdate>2009</risdate><spage>2405</spage><epage>2408</epage><pages>2405-2408</pages><issn>0271-4302</issn><eissn>2158-1525</eissn><isbn>1424438276</isbn><isbn>9781424438273</isbn><eisbn>1424438284</eisbn><eisbn>9781424438280</eisbn><abstract>In this paper, an integrated DC-DC (Buck) converter is presented. The Buck converter accepts input voltage in the range 2.7-5.5 V while using 2.5 V devices. A low drop-out (LDO) regulator is used to limit the maximum input voltage to the DCDC switches to protect it against overvoltage breakdown. 5 MHz switching frequency is used to allow using smaller external inductors. The Buck converter is implemented in TSMC 65 nm CMOS technology and it occupies 0.15 mm 2 while the LDO regulator, bandgap, clock generator and bias circuits occupy 0.19 mm 2 . Up to 88% and 77% efficiency is achieved at 2.5 V and 1.2 V output, respectively, using 3.6 V input. If the input voltage is limited to 3.3 V, the LDO regulator is bypassed, and the peak efficiency becomes 92% for 2.5 V and 85% for 1.2 V output.</abstract><pub>IEEE</pub><doi>10.1109/ISCAS.2009.5118285</doi><tpages>4</tpages></addata></record> |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Breakdown voltage Buck converters CMOS technology DC-DC power converters Inductors Protection Regulators Switches Switching frequency Voltage control |
title | High voltage tolerant integrated Buck converter in 65nm 2.5V CMOS |
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