High voltage tolerant integrated Buck converter in 65nm 2.5V CMOS

In this paper, an integrated DC-DC (Buck) converter is presented. The Buck converter accepts input voltage in the range 2.7-5.5 V while using 2.5 V devices. A low drop-out (LDO) regulator is used to limit the maximum input voltage to the DCDC switches to protect it against overvoltage breakdown. 5 MHz switching frequency is used to allow using smaller external inductors. The Buck converter is implemented in TSMC 65 nm CMOS technology and it occupies 0.15 mm 2 while the LDO regulator, bandgap, clock generator and bias circuits occupy 0.19 mm 2 . Up to 88% and 77% efficiency is achieved at 2.5 V and 1.2 V output, respectively, using 3.6 V input. If the input voltage is limited to 3.3 V, the LDO regulator is bypassed, and the peak efficiency becomes 92% for 2.5 V and 85% for 1.2 V output.