A low jitter arbitrary-input pulsewidth control loop with wide duty cycle adjustment

An arbitrary-input pulsewidth control loop (AIPWCL) based on a delay-locked loop with duty cycle corrector is presented. The duty cycles of the clock signals can be adjusted from 10% to 90% in 10% steps. The proposed AIPWCL is designed and simulated by using tsmc 0.13 mum CMOS process. The operation...

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Bibliographische Detailangaben

Hauptverfasser:	Ro-Min Weng, Yun-Chih Lu, Chun-Yu Liu
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Charge pumps Circuits Clocks Delay Frequency Jitter Partial discharges Signal generators Space vector pulse width modulation Voltage
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