A low jitter arbitrary-input pulsewidth control loop with wide duty cycle adjustment

An arbitrary-input pulsewidth control loop (AIPWCL) based on a delay-locked loop with duty cycle corrector is presented. The duty cycles of the clock signals can be adjusted from 10% to 90% in 10% steps. The proposed AIPWCL is designed and simulated by using tsmc 0.13 mum CMOS process. The operation frequency range is from 770 MHz to 1.05 GHz. The locking time of AIPWCL is less than 40 ns within the operation frequency band. The power dissipation is 4.38 mW at 1.2 V voltage supply. The peak-to-peak jitter is less than 1 ps at an input clock frequency of 1 GHz while adjusting various duty cycles.